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this is information on a product in full production. november 2013 docid17659 rev 9 1/131 stm32l15xx6/8/b ultra-low-power 32-bit mcu arm-based cortex-m3, 128kb flash, 16kb sram, 4kb eeprom, lcd, usb, adc, dac datasheet - production data features ? ultra-low-power platform ? 1.65 v to 3.6 v power supply ? -40c to 85c/105c temperature range ? 0.3 a standby mode (3 wakeup pins) ? 0.9 a standby mode + rtc ? 0.57 a stop mode (16 wakeup lines) ? 1.2 a stop mode + rtc ? 9 a low-power run mode ? 214 a/mhz run mode ? 10 na ultra-low i/o leakage ? < 8 s wakeup time ? core: arm ? cortex ? -m3 32-bit cpu ? from 32 khz up to 32 mhz max ? 33.3 dmips peak (dhrystone 2.1) ? memory protection unit ? reset and supply management ? ultra-safe, low-po wer bor (brownout reset) with 5 selectable thresholds ? ultra-low-power por/pdr ? programmable voltage detector (pvd) ? clock sources ? 1 to 24 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? high speed internal 16 mhz factory- trimmed rc (+/- 1%) ? internal low power 37 khz rc ? internal multispeed low power 65 khz to 4.2 mhz ? pll for cpu clock and usb (48 mhz) ? pre-programmed bootloader ? usart supported ? development support ? serial wire debug supported ? jtag and trace supported ? up to 83 fast i/os (7 3 i/os 5v tolerant), all mappable on 16 external interrupt vectors ? memories ? up to 128 kb flash with ecc ? up to 16 kb ram ? up to 4 kb of true eeprom with ecc ? 80 byte backup register ? lcd driver for up to 8x40 segments ? support contrast adjustment ? support blinking mode ? step-up converter on board ? rich analog peripherals (down to 1.8 v) ? 12-bit adc 1 msps up to 24 channels ? 12-bit dac 2 channels with output buffers ? 2x ultra-low-power-comparators (window mode and wa ke up capability) ? dma controller 7x channels ? 8x peripherals communication interface ? 1x usb 2.0 (internal 48 mhz pll) ? 3x usart (iso 7816, irda) ? 2x spi 16 mbits/s ? 2x i2c (smbus/pmbus) ? 10x timers: 6x 16-bit with up to 4 ic/oc/pwm channels, 2x 16-bit basic timer, 2x watchdog timers (independent and window) ? up to 20 capacitive sensing channels supporting touchkey, li near and rotary touch sensors ? crc calculation unit, 96-bit unique id table 1. device summary reference part number stm32l151x6/8/b stm32l151cb, stm32l151c8, stm32l151c6, stm32l151rb, stm32l151r8, stm32l151r6, stm32l151vb, stm32l151v8 stm32l152x6/.8/b stm32l152cb, stm32l152c8, stm32l152c6, stm32l152rb, stm32l152r8, stm32l152r6, stm32l152vb, stm32l152v8 lqfp100 14 14 mm lqfp64 10 10 m m lqfp48 7 7 mm bga100 7 7 mm bga64 5 5 mm ufqfpn48 7 7 mm www.st.com
contents stm32l151x6/8/b, stm32l152x6/8/b 2/131 docid17659 rev 9 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 ultralow power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 arm cortex-m3 core with mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.4 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22 3.6 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 dma (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 lcd (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10 adc (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 ultralow power comparators and reference voltage . . . . . . . . . . . . . . . . . 25 3.13 routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.15 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
docid17659 rev 9 3/131 stm32l151x6/8/b, stm32l152x6/8/b contents 4 3.15.1 general-purpose timers (tim2, tim3, tim4, tim9, tim10 and tim11) . 27 3.15.2 basic timers (tim6 and tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15.3 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16.1 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16.2 universal synchronous/asynchronous receiver transmitter (usart) . . 28 3.16.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16.4 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 29 3.18 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.7 optional lcd power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.8 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.2 embedded reset and power control bloc k characteristics . . . . . . . . . . . 53 6.3.3 embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.5 wakeup time from low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.7 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
contents stm32l151x6/8/b, stm32l152x6/8/b 4/131 docid17659 rev 9 6.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.11 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.12 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.13 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.14 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.15 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.16 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.17 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.18 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.19 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.20 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.21 lcd controller (stm32l152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
docid17659 rev 9 5/131 stm32l151x6/8/b, stm32l152x6/8/b list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. ultralow power stm32l15xxx dev ice features and peripheral counts . . . . . . . . . . . . . . . . 10 table 3. functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14 table 4. cpu frequency range depending on dynamic voltag e scaling . . . . . . . . . . . . . . . . . . . . . . 15 table 5. working mode-dependent functionalities (from run/active down to standby) . . . . . . . . . . 16 table 6. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 8. stm32l15xxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 9. alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 10. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 11. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 12. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 13. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 14. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 15. embedded internal reference voltage calibration valu es . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 table 17. current consumption in run mode, code with data processing running from flash. . . . . . 57 table 18. current consumption in run mode, code wit h data processing running from ram . . . . . . 58 table 19. current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 20. current consumption in low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 21. current consumption in low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 22. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . . 63 table 23. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 65 table 24. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 25. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 26. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 27. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 28. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 29. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 30. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 31. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 32. msi oscillator ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 33. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 34. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 35. flash memory and dat a eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 36. flash memory, data eeprom endurance and data retention . . . . . . . . . . . . . . . . . . . . . . 78 table 37. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 38. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 39. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 40. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 41. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 42. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 43. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 44. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 45. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 46. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 47. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 48. scl frequency (f pclk1 = 32 mhz, v dd = vdd_i2c = 3.3 v). . . . . . . . . . . . . . . . . . . . . . . . 89
list of tables stm32l151x 6/8/b, stm32l152x6/8/b 6/131 docid17659 rev 9 table 49. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 50. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 51. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 52. usb: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 53. adc clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 54. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 55. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 56. r ain max for f adc = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 57. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 58. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 59. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 table 60. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 61. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 62. lcd controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 63. lqpf100 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 64. lqfp64 10 x 10 mm 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 111 table 65. lqfp48 7 x 7 mm, 48-pin low-profile quad fl at package mechanical data. . . . . . . . . . . . 113 table 66. ufqfpn48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 67. ufbga100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 68. tfbga64 5.0x5.0x1.2 mm, 0.5 mm pitch thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 69. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 70. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 71. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
docid17659 rev 9 7/131 stm32l151x6/8/b, stm32l152x6/8/b list of figures 7 list of figures figure 1. ultralow power stm32l15xxx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3. stm32l15xvx ufbga100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 4. stm32l15xvx lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 5. stm32l15xrx tfbga64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 6. stm32l15xrx lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 7. stm32l15xcx lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 8. stm32l15xcx ufqfpn48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 9. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 12. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 13. optional lcd power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 14. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 15. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 16. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 17. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 18. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 19. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 20. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 21. i 2 c bus ac waveforms and measurement ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 22. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 23. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 24. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 25. usb timings: definition of data signal rise and fa ll time . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 26. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 27. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 28. maximum dynamic current consumption on v ref+ supply pin during adc conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 29. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 99 figure 30. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . . 99 figure 31. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 32. lqfp100 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 107 figure 33. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 34. lqfp64 10 x 10 mm, 64-pin low-profile quad fl at package outline . . . . . . . . . . . . . . . . . 110 figure 35. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 36. lqfp48 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 112 figure 37. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 38. ufqfpn48 7 x 7 mm 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 39. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 40. ufbga100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 41. tfbga64 - 5.0x5. 0x1.2 mm, 0.5 mm pitch, thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 42. recommended pcb design rules for pads (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . . . 120 figure 43. thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
introduction stm32l151x6/8/b, stm32l152x6/8/b 8/131 docid17659 rev 9 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32l151xx and stm32l152xx ultralow power arm cortex-m3 based microcontrollers product line. the ultralow power stm32l15xxx family includes devices in 3 different package types: from 48 to 100 pins. depending on the device chosen, different sets of peripherals are included, the description below gives an overview of t he complete range of peripherals proposed in this family. these features make the ultralow power stm3 2l15xxx microcontroller fa mily suitable for a wide range of applications: ? medical and handheld equipment ? application control and user interface ? pc peripherals, gaming, gps and sport equipment ? alarm systems, wired and wireless sensors, video intercom ? utility metering this stm32l151xx and stm32l152xx datasheet should be read in conjunction with the stm32l1xxxx reference manual (rm0038). the document "getting started with stm32l1xxx hardware development? an3216 gives a hardware implementation overview. the both documents are available from the stmicroelectronics website www.st.com. for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/inde x.jsp?topic=/com.arm.doc.ddi0337g. figure 1 shows the general block diagram of the device family.
docid17659 rev 9 9/131 stm32l151x6/8/b, stm32l152x6/8/b description 47 2 description the ultralow power stm32l15xxx incorporates the connectivity power of the universal serial bus (usb) with the high-performance ar m cortex-m3 32-bit risc core operating at a 32 mhz frequency, a memory protection un it (mpu), high-speed embedded memories (flash memory up to 128 kbytes and ram up to 16 kbytes) and an extensive range of enhanced i/os and peripherals connected to two apb buses. all devices offer a 12-bit adc, 2 dacs and 2 ultralow power comparators, six general- purpose 16-bit timers and two basic time rs, which can be used as time bases. moreover, the stm32l15xxx devices contai n standard and advanced communication interfaces: up to two i 2 cs and spis, three usarts and a usb. the stm32l15xxx devices offer up to 20 capacitive sensin g channels to simply add touch sensing functionality to any application. they also include a real-time clock and a set of backup registers that remain powered in standby mode. finally, the integrated lcd controller has a built-in lcd voltage generator that allows you to drive up to 8 multiplexed lcds with contrast independent of the supply voltage. the ultralow power stm32l15xxx operates fr om a 1.8 to 3.6 v power supply (down to 1.65 v at power down) with bor and from a 1.65 to 3.6 v power supply without bor option. it is available in the -40 to +85 c temperature range, extended to 105c in low power dissipation state. a comprehensive set of po wer-saving modes allows the design of low- power applications.
description stm32l151x6/8/b, stm32l152x6/8/b 10/131 docid17659 rev 9 2.1 device overview table 2. ultralow power stm32l15xxx device features and peripheral counts peripheral stm32l15xcx stm32l15xrx stm32l15xvx flash (kbytes) 32 64 128 32 64 128 64 128 data eeprom (kbytes) 4 ram (kbytes) 10 10 16 10 10 16 10 16 timers general- purpose 6 basic 2 communication interfaces spi 2 i 2 c 2 usart 3 usb 1 gpios 37 51 83 12-bit synchronized adc number of channels 1 14 channels 1 20 channels 1 24 channels 12-bit dac number of channels 2 2 lcd (stm32l152xx only) com x seg 4x18 4x32 8x28 4x44 8x40 comparator 2 capacitive sensing channels 13 20 max. cpu frequency 32 mhz operating voltage 1.8 v to 3.6 v (down to 1.65 v at power-down) with bor option 1.65 v to 3.6 v without bor option operating temperatures ambient temperatures: ?40 to +85 c junction temperature: ?40 to + 105 c packages lqfp48, ufqfpn48 lqfp64, bga64 lqfp100, bga100
docid17659 rev 9 11/131 stm32l151x6/8/b, stm32l152x6/8/b description 47 2.2 ultralow power device continuum the ultralow power stm32l151xx and stm32l152xx are fully pin-to-pin and software compatible. besides the full compatibility within th e family, the devices are part of stmicroelectronics microcontrollers ultralow power strategy which also includes stm8l101xx and stm8l15xx devices. th e stm8l and stm32l families allow a continuum of performance, peripherals , system architecture and features. they are all based on stmicroelectronics ultralow leakage process. note: the ultralow power stm3 2l and general-purpose stm32f xxxx families are pin-to-pin compatible. the stm8l15xxx devices are pin-to-pin compatible with the stm8l101xx devices. please refer to the stm32f and stm8l documentation for more information on these devices. 2.2.1 performance all families incorpor ate highly energy-efficient cores with both harvard architecture and pipelined execution: advanced stm8 core fo r stm8l families and ar m cortex-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultralow power performance to range from 5 up to 33.3 dmips. 2.2.2 shared peripherals stm8l15xxx and stm32l1xxxx share identical peripherals which ensure a very easy migration from one family to another: ? analog peripherals: adc, dac and comparators ? digital peripherals: rtc and some communication interfaces 2.2.3 common system strategy to offer flexibility and optim ize performance, the stm8l 15xx and stm32l1xxxx families use a common architecture: ? same power supply range from 1.65 v to 3.6 v, (1.65 v at power down only for stm8l15xx devices) ? architecture optimized to reach ultralow consumption both in low power modes and run mode ? fast startup strategy from low power modes ? flexible system clock ? ultrasafe reset: same reset strategy including powe r-on reset, power-down reset, brownout reset and programmable voltage detector. 2.2.4 features st ultralow power continuum al so lies in feature compatibility: ? more than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm ? memory density ranging from 4 to 384 kbytes
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 12/131 docid17659 rev 9 3 functional overview figure 1 shows the block diagrams. figure 1. ultralow powe r stm32l15xxx block diagram 1. af = alternate function on i/o port pin. ext. it wwdg 12-bit adc jtag &sw 24 a f jt d i jt ck/ s wclk jtms /s wdat njt r st jtdo nrst v dd =1. 65 v to 3. 6 v 83a f ah b2 us b_dp us b_dm mo s i,mis o, s ck, ns s wku p f ma x :32 mhz v ss s c l, sd a, smb u s ,p mb u s i2c 2 v ddref _adc * gp dma tim2 tim3 x t al o s c 1-24 mhz x t a l 32 khz osc_in osc_out os c32 _out os c32 _in pll & apb1 : f ma x =32mhz a hbp cl k hc l k clock management ap bp cl k as af as af volt. reg. v co r e po we r as a f tim4 b us matrix int erface rt c rc hs ibus db us pbus obl flash us b ram 512 b us art 1 us art 2 sp i2 7 c h annels sc l, s d a i2c 1 as af rx ,t x , ct s , rt s , us art 3 te mp s ens or v ss ref_ adc * ahb:f max =32 mhz 4channels 4channels 4channels fc lk iwdg @v dd supply monitoring @v dd a vdda / vss a @v dd a s m artc ard a s af rx ,t x , c t s, r t s, s m ar tc ar d as af rx ,tx, c t s, r t s, s m artca rd as a f ap b2 : f ma x =32 mhz nv ic spi 1 mosi ,mis o, sc k, ns s as af if @vd d a pv d power reset int ahb 2 aw u @v dd a rtc_out, rtc_ts,rtc_tamp system p a [15:0 ] p b [15:0 ] p c [15:0 ] pd[ 15:0] pe[1 5:0 ] lcd 8x4 0 (4x44 ) seg x com x if if if @v dd a dac_out1 as af mp u co m p 2 comp2 _in- /in+ co m p 1 tim6 tim7 m ti m9 ti m10 ti m11 2 channe ls 1 c h annel 1 channel general purpose timers 128 kb flash 4 kb data eeprom lcd step-up converter v lcd = 2.5 v to 3.6 v v lc d ba si c t ime rs rtc_afin vr ef o utpu t ai15687h cortex-m3 cpu trace controller etm ram 16 kb 12-bit dac1 12-bit dac2 gpioa gpiob gpioc gpiod gpioe traceck, traced0, traced1, traced2, traced3 rc ms rc ls standby interface backup interface usb 2.0 fs device bor/v refint power-up/ power-down backup register ph[2 :0 ] gpioh dac_out2 as af ahb/apb2 ahb/apb1
docid17659 rev 9 13/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 3.1 low power modes the ultralow power stm32l15xxx supports dy namic voltage scaling to optimize its power consumption in run mode. the voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system?s maximum operating frequency and the external voltage supply: ? in range 1 (v dd range limited to 1.71-3.6 v), the cpu runs at up to 32 mhz (refer to table 17 for consumption). ? in range 2 (full v dd range), the cpu runs at up to 16 mhz (refer to table 17 for consumption) ? in range 3 (full v dd range), the cpu runs at up to 4 mhz (generated only with the multispeed internal rc oscilla tor clock source). refer to table 17 for consumption. seven low power modes are provided to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. sleep mode power consumption: refer to table 19 . ? low power run mode this mode is achieved with the multispeed internal (msi) rc os cillator set to the minimum clock (65 khz), execution from sram or flash memory, and internal regulator in low power mode to minimize the regulator's operating curren t. in the low power run mode, the clock frequency and the number of enabled peripherals are both limited. low power run mode consumption: refer to table 20: current consumption in low power run mode . ? low power sleep mode this mode is achieved by entering the sleep mode with the internal voltage regulator in low power mode to minimize the regulator?s operating current. in the low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 khz. when wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. low power sleep mode consumption: refer to table 21: current consumption in low power sleep mode . ? stop mode with rtc stop mode achieves the lowest power consumption while retaining the ram and register contents and real time clock. all clocks in the v core domain are stopped, the pll, msi rc, hsi rc and hse crystal oscillato rs are disabled. the lse or lsi is still running. the voltage regulato r is in the low power mode. the device can be woken up from stop mode by any of the exti line, in 8 s. the exti line source can be one of the 16 external lines. it can be the pvd output, the comparator 1 event or comparator 2 event (if internal reference voltage is on), it can be the rtc alarm(s), the usb wakeup, the rtc tamper events, the rtc timestamp event or the rtc wakeup. ? stop mode without rtc stop mode achieves the lowest power consumption while retaining the ram and register contents. all clocks are stopped, the pll, msi rc, hsi and lsi rc, lse and
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 14/131 docid17659 rev 9 hse crystal oscillators are disabled. the vo ltage regulator is in the low power mode. the device can be woken up from stop mode by any of the exti line, in 8 s. the exti line source can be one of the 16 external lines. it can be the pvd output, the comparator 1 event or comparator 2 event (if internal reference voltage is on). it can also be wakened by the usb wakeup. stop mode consumption: refer to table 22: typical and maximum current consumptions in stop mode . ? standby mode with rtc standby mode is used to achieve the lowest power consumption and real time clock. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hsi rc and hse crystal oscillators are also switched off. the lse or lsi is still running. after entering standby mode, the ram and register contents are lost except fo r registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32k osc, rcc_csr). the device exits standby mode in 60 s when an external reset (nrst pin), an iwdg reset, a rising edge on one of the three wkup pins, rtc alarm (alarm a or alarm b), rtc tamper event, rtc timestamp event or rtc wakeup event occurs. ? standby mode without rtc standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi, rc, hsi and lsi rc, hse and lse crystal os cillators are also switched off. after entering standby mode, the ram and register contents are lost except for registers in the standby circuitry (wakeup logic, iw dg, rtc, lsi, lse crystal 32k osc, rcc_csr). the device exits standby mode in 60 s when an external reset (nrst pin) or a rising edge on one of the three wkup pin occurs. standby mode consumption: refer to table 23 . note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering the stop or standby mode. table 3. functionalities depending on the operating power supply range operating power supply range functionalities depending on the operating power supply range dac and adc operation usb dynamic voltage scaling range i/o operation v dd = 1.65 to 1.71 v not functional not functional range 2 or range 3 degraded speed performance v dd = 1.71 to 1.8 v (1) not functional not functional range 1, range 2 or range 3 degraded speed performance v dd = 1.8 to 2.0 v (1) conversion time up to 500 ksps not functional range 1, range 2 or range 3 degraded speed performance
docid17659 rev 9 15/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 v dd = 2.0 to 2.4 v conversion time up to 500 ksps functional (2) range 1, range 2 or range 3 full speed operation v dd = 2.4 to 3.6 v conversion time up to 1 msps functional (2) range 1, range 2 or range 3 full speed operation 1. the cpu frequency changes from in itial to final must respect "f cpu initial < 4*f cpu final" to limit v core drop due to current consumption peak when frequency increases. it must also re spect 5 s delay between two changes. for example to switch from 4.2 mhz to 32 mhz, you can switch from 4.2 mhz to 16 mhz, wait 5 s, then switch from 16 mhz to 32 mhz. 2. should be usb compliant from i/o voltage standpoint, the minimum v dd is 3.0 v. table 4. cpu frequency range de pending on dynamic voltage scaling cpu frequency range dynamic voltage scaling range 16 mhz to 32 mhz (1ws) 32 khz to 16 mhz (0ws) range 1 8 mhz to 16 mhz (1ws) 32 khz to 8 mhz (0ws) range 2 2.1 mhz to 4.2 mhz (1ws) 32 khz to 2.1 mhz (0ws) range 3 table 3. functionalities depending on the operating power supply range (continued) operating power supply range functionalities depending on the operating power supply range dac and adc operation usb dynamic voltage scaling range i/o operation
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 16/131 docid17659 rev 9 table 5. working mode-dep endent functionalities ( from run/active down to stand by) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability cpu y - y - - - - - flash y y y n - - - - ram y y y y y - - - backup registers y y y y y - y - eeprom y - y y y - - - brown-out rest (bor) yyyyyyy- dma y y y y - - - - programmable voltage detector (pvd) yyyyyyy- power on reset (por) yyyyyyy- power down rest (pdr) yyyyy-y- high speed internal (hsi) yy------ high speed external (hse) yy------ low speed internal (lsi) yyyyy--- low speed external (lse) yyyyy--- multi-speed internal (msi) yyyy---- inter-connect controller yyyy---- rtc y y y y y y y - rtc tamper y y y y y y y y auto wakeup (awu) yyyyyyyy lcd y y y y y - - - usb y y - - - y - - usart y y y y y (1) -- spi y y y y - - - - i2c y y y y - (1) -- adc y y - - - - - -
docid17659 rev 9 17/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 3.2 arm cortex-m3 core with mpu the arm cortex-m3 processor is the industry leading processor for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the memory protection unit (mpu) improves system reliability by defining the memory attributes (such as read/write access permissions ) for different memory regions. it provides up to eight different regions and an optional predefined background region. owing to its embedded arm core, the stm32l15 xxx is compatible with all arm tools and software. dac y y y y y - - - temperature sensor yyyyy--- comparators y y y y y y - - 16-bit and 32-bit timers yyyy---- iwdg y y y y y y y y wwdg y y y y - - - - touch sensing y - - - - - - - systick timer y y y y - - - - gpios y y y y y y - 3 pins wakeup time to run mode 0 s 0.36 s 3 s 32 s < 8 s 50 s consumption v dd =1.8v to 3.6v (typ) d o w n t o 214 a/mhz (from flash) d o w n t o 50 a/mhz (from flash) down to 9 a down to 4.4 a 0.5 a (no rtc) v dd =1.8v 0.3 a (no rtc) v dd =1.8v 1.4 a (with rtc) v dd =1.8v 1 a (with rtc) v dd =1.8v 0.5 a (no rtc) v dd =3.0v 0.3 a (no rtc) v dd =3.0v 1.6 a (with rtc) v dd =3.0v 1.3 a (with rtc) v dd =3.0v 1. the startup on communication line wakes the cpu which wa s made possible by an exti, th is induces a delay before entering run mode. table 5. working mode-dependent functionalities ( from run/active down to stand by) (continued) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 18/131 docid17659 rev 9 nested vectored interrupt controller (nvic) the ultralow power stm32l15xxx embeds a nested vectored interrupt controller able to handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving , higher-priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.3 reset and supply management 3.3.1 power supply schemes ? v dd = 1.65 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. ? v ssa , v dda = 1.65 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 1.8 v when the adc is used). v dda and v ssa must be connected to v dd and v ss , respectively. 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr) that can be coupled with a brownout reset (bor) circuitry. the device exists in two versions: ? the version with bor activated at power-on operates between 1.8 v and 3.6 v. ? the other version without bor oper ates between 1.65 v and 3.6 v. after the v dd threshold is reached (1.65 v or 1.8 v depending on the bor which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the bor permanently: in this case, the v dd min value becomes 1.65 v (whatever the version, bo r active or not, at power-on). when bor is active at power- on, it ensures proper operation starting from 1.8 v whatever the power ramp-up phase before it reaches 1.8 v. when bor is not active at power-up, the power ramp-up should guarantee that 1.65 v is reached on v dd at least 1 ms after it exits the por area.
docid17659 rev 9 19/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 five bor thresholds are available through opti on bytes, starting from 1.8 v to 3 v. to reduce the power consumption in stop mode, it is possible to automatically switch off the internal reference voltage (v refint ) in stop mode. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. note: the start-up time at power-on is typically 3.3 ms when bor is active at power-up, the start- up time at power-on can be decreased down to 1 ms typically for devices with bor inactive at power-up. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.3.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. ? mr is used in run mode (nominal regulation) ? lpr is used in the low-power run, low-power sleep and stop modes ? power down is used in standby mode. the regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and ram are lost are lost except for the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32k osc, rcc_csr). 3.3.4 boot modes at startup, boot pins are used to select one of three boot options: ? boot from flash memory ? boot from system memory ? boot from embedded ram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 or usart2. see stm32? microcontroller system memory boot mode an2606 for details.
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 20/131 docid17659 rev 9 3.4 clock management the clock controller distributes the clocks coming from different oscillators to the core and the peripherals. it also manages clock gati ng for low power modes and ensures clock robustness. it features: ? clock prescaler : to get the best trade-off between speed and current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler ? safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? master clock source : three different clock sources can be used to drive the master clock: ? 1-24 mhz high-speed external crystal (hse), that can supply a pll ? 16 mhz high-speed internal rc oscillator (h si), trimmable by software, that can supply a pll ? multispeed internal rc oscilla tor (msi), trimmable by soft ware, able to generate 7 frequencies (65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.1 mhz, 4.2 mhz) with a consumption proportional to speed, down to 750 na typical. when a 32.768 khz clock source is available in the system (lse), the msi frequency can be trimmed by software down to a 0.5% accuracy. ? auxiliary clock source : two ultralow power clock sources that can be used to drive the lcd controller and the real-time clock: ? 32.768 khz low-speed external crystal (lse) ? 37 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock can be measured using the high-speed internal rc oscillator for greater precision. ? rtc and lcd clock sources: the lsi, lse or hse sources can be chosen to clock the rtc and the lcd, whatever the system clock. ? usb clock source: the embedded pll has a dedicated 48 mhz clock output to supply the usb interface. ? startup clock : after reset, the microcontroller restarts by default with an internal 2.1 mhz clock (msi). the prescaler ratio an d clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the master cl ock is automatically switched to hsi and a software interrupt is generated if enabled. ? clock-out capability (mco: microcontroller clock output): it outputs one of the internal clocks for external use by the application. several prescalers allow t he configuration of the ahb frequency, the high-speed apb (apb2) and the low-sp eed apb (apb1) domains. the maxi mum frequency of the ahb and the apb domains is 32 mhz. see figure 2 for details on the clock tree.
docid17659 rev 9 21/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 figure 2. clock tree 1. for the usb function to be available, both hse and pll must be enabled, with the cpu running at either 24 mhz or 32 mhz. ahb prescaler /1, 2..512 apb1 prescaler /1, 2, 4, 8, 16 pclk1 hclk to ahb bus, core, memory and dma peripherals to apb1 peripheral clock enable enable peripheral clock apb2 prescaler /1, 2, 4, 8, 16 pclk2 to tim9, 10, and 11 peripherals to apb2 peripheral clock enable enable peripheral clock 32 mhz max 32 mhz max to cortex system timer /8 clock enable sysclk timxclk timxclk fclk cortex free running clock to tim2,3,4,6 and 7 if (apb1 prescaler =1) x1 else x2 if (apb2 prescaler =1) x1 else x2 32 mhz max hse osc 1-24 mhz osc_in osc_out hsi rc 16 mhz x3,x4,x6,x8 x12,x16,x24 pllmul pllclk hsi hsi hse pllsrc sw css x32,x48 /2,/3,/4 48 mhz usbclk to usb interface plldiv to adc peripheral clock enable adcclk mhz max 32 osc32_in osc32_out lse osc 32.768 khz lsi rc 37 khz to independent watchdog (iwdg) mco pllclk hsi hse lse lsi /2,4, 8,16 to rtc mcosel rtcclk rtcsel[1:0] iwdgclk sysclk /1,2,4, 8,16 msi lse lsi to lcd to timer 9, 10, 11 etr hse = high-speed external clock signal lse = low -speed external clock signal lsi = low-speed internal clock signal hsi = high-speed internal clock signal legend : ai17212c ms i = multispeed internal clock signal pllvco/2 msi rc msi
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 22/131 docid17659 rev 9 3.5 low power real-time clock and backup registers the real-time clock (rtc) is an independent bc d timer/counter. dedica ted registers contain the second, minute, hour (12/24 hour), week da y, date, month, year, in bcd (binary-coded decimal) format. correction for 28, 29 (leap ye ar), 30, and 31 day of the month are made automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. ? the programmable wakeup time ranges from 120 s to 36 hours ? stop mode consumption with lsi and auto-wak eup: 1.2 a (at 1.8 v) and 1.4 a (at 3.0 v) ? stop mode consumption with lse, calendar an d auto-wakeup: 1.3 a (at 1.8v), 1.6 a (at 3.0 v) the rtc can be calibrated with an external 512 hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. there are twenty 32-bit backup registers provided to store 80 bytes of user application data. they are cleared in case of tamper detection. 3.6 gpios (general-pur pose inputs/outputs) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated afio registers. all gpios are high current capable. the alternate function configuration of i/os can be locked if needed following a specific sequence in order to avoid spurious writing to the i/o registers. the i/o controller is connected to the ahb with a toggling speed of up to 16 mhz. external interrupt/event controller (exti) the external interrupt/event controller consists of 23 edge detector lines used to generate interrupt/event requests. each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the in ternal apb2 clock period. up to 83 gpios can be connected to the 16 external interrupt lines. the 7 other lines are connected to rtc, pvd, usb or comparator events.
docid17659 rev 9 23/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 3.7 memories the stm32l15xxx devices have the following features: ? up to 16 kbyte of embedded ram accessed (read/write) at cpu clock speed with 0 wait states. with the enhanced bus matrix, operating the ram does not lead to any performance penalty during accesses to th e system bus (ahb and apb buses). ? the non-volatile memory is divided into three arrays: ? 32, 64 or 128 kbyte of embedded flash program memory ? 4 kbyte of data eeprom ? options bytes the options bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, th e flash memory cannot be read from or written to if either debug features ar e connected or boot in ram is selected ? level 2: chip readout protection, debug f eatures (cortex-m3 jtag and serial wire) and boot in ram selection disabled (jtag fuse) the whole non-volatile memory embeds the error correction code (ecc) feature. 3.8 dma (direct memory access) the flexible 7-channel, general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose timers and adc. 3.9 lcd (liquid crystal display) the lcd drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. ? internal step-up converter to guarantee functi onality and contrast control irrespective of v dd . this converter can be deactivated, in which case the v lcd pin is used to provide the voltage to the lcd ? supports static, 1/2, 1/3, 1/4 and 1/8 duty ? supports static, 1/2, 1/3 and 1/4 bias ? phase inversion to reduce power consumption and emi ? up to 8 pixels can be programmed to blink ? unneeded segments and common pins can be used as general i/o pins ? lcd ram can be updated at any time owing to a double-buffer ? the lcd controller can operate in stop mode
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 24/131 docid17659 rev 9 3.10 adc (analog-to-digital converter) a 12-bit analog-to-digital converters is em bedded into stm32l15xxx devices with up to 24 external channels, performing conversions in single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) can be internally connected to the adc start trigger and injection trigger, to allow the application to synchronize a/d conversions and timers. an injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task. the adc includes a specific lo w power mode. the converter is able to operate at maximum speed even if the cpu is operating at a very low frequency and has an auto-shutdown function. the adc?s runtime and analog front- end current consumpti on are thus minimized whatever the mcu operating mode. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode, see table 58: temperature sensor calibration values . 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally con nected to the adc_in17 input channel. it enables accurate monitoring of the v dd value (when no external voltage, vref+, is available for adc). the precise voltage of v refint is individually measured for each part by st during production test and stored in the s ystem memory area. it is accessible in read- only mode see table 16: embedded internal reference voltage . 3.11 dac (digital-to-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration.
docid17659 rev 9 25/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 this dual digital interface supports the following features: ? two dac converters: one for each output channel ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channels? independent or simultaneous conversions ? dma capability for each channel (i ncluding the unde rrun in terrupt) ? external triggers for conversion ? input reference voltage v ref+ eight dac trigger inputs are used in the stm32l15xxx. the dac channels are triggered through the timer update outputs that are also connected to different dma channels. 3.12 ultralow power comparat ors and reference voltage the stm32l15xxx embeds tw o comparators sharing the same current bias and reference voltage. the reference voltage can be internal or external (coming from an i/o). ? one comparator with fixed threshold ? one comparator with rail-to-rail inputs, fast or slow mode. the threshold can be one of the following: ? dac output ? external i/o ? internal reference voltage (v refint ) or v refint submultiple (1/4, 1/2, 3/4) both comparators can wake up from stop mode, and be combined into a window comparator. the internal reference voltage is available externally via a low power / low current output buffer (driving current capability of 1 a typical). 3.13 routing interface this interface controls the internal routin g of i/os to tim2, tim3, tim4 and to the comparator and reference voltage output. 3.14 touch sensing the stm32l15xxx devices provide a simple solution fo r adding capacitive sensing functionality to any application. these device s offer up to 20 capacitive sensing channels distributed over 10 analog i/o groups. only soft ware capacitive sensing acquisition mode is supported. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). the capacitive variation introduced by the finger (or any conduct ive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 26/131 docid17659 rev 9 into a sampling capacitor unt il the voltage across this capa citor has reached a specific threshold. the capacitive sensing acquisition only requires few external components to operate. reliable touch sensing functionality can be quickly and easily implemented using the free stm32l1xx stmtouch touch sensing firmware library. 3.15 timers and watchdogs the ultralow power stm32l15xxx devices incl ude six general-purpose timers, two basic timers and two watchdog timers. table 6 compares the features of the general-purpose and basic timers. table 6. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim2, tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim9 16-bit up any integer between 1 and 65536 no 2 no tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no
docid17659 rev 9 27/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 3.15.1 general-purpose timers (tim2, tim3, tim4, tim9, tim10 and tim11) there are six synchronizable general-purpose timers embedded in the stm32l15xxx devices (see table 6 for differences). tim2, tim3, tim4 these timers are based on a 16-bit auto-reloa d up/down-counter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output compare, pwm or one- pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2, tim3, tim4 general-purpose timers can work together or with the tim10, tim11 and tim9 general-purpose timers via the time r link feature for synchronization or event chaining. their counter can be frozen in debu g mode. any of the general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4 all have independent dma request generation. these timers are capable of handling quadrat ure (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. tim10, tim11 and tim9 these timers are based on a 16-bit auto-reloa d up-counter and a 16-bit prescaler. they include a 16-bit prescaler. tim10 and tim11 feature one independent channel, whereas tim9 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4 full-featured general- purpose timers. they can also be used as simple time bases and be clocked by the lse clock source (32.768 khz) to provide time bases independent from the main cpu clock. 3.15.2 basic timers (tim6 and tim7) these timers are mainly used for dac trigger g eneration. they can also be used as generic 16-bit time bases. 3.15.3 systick timer this timer is dedicated to the os, but could also be used as a standard downcounter. it is based on a 24-bit down-count er with autoreload capability and a programmable clock source. it features a maskable system interr upt generation when the counter reaches 0. 3.15.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit down-counter and 8-bit prescaler. it is clocked from an independent 37 khz internal rc and, as it operates independently of the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode.
functional overview stm32l1 51x6/8/b, stm32l152x6/8/b 28/131 docid17659 rev 9 3.15.5 window watchdog (wwdg) the window watchdog is based on a 7-bit down-c ounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.16 communication interfaces 3.16.1 i2c bus up to two i2c bus interfaces can operate in multimaster and slave mo des. they can support standard and fast modes. they support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. a hardware crc generation/verification is embedded. they can be served by dma and they support sm bus 2.0/pm bus. 3.16.2 universal synchronous/asynchr onous receiver tran smitter (usart) all usart interfaces are able to communicate at speeds of up to 4 mbit/s. they provide hardware management of the cts and rts signals. they support irda sir endec, are iso 7816 compliant and have lin master/slave capability. all usart interfaces can be served by the dma controller. 3.16.3 serial peripheral interface (spi) up to two spis are able to communicate at up to 16 mbits/s in slave and master modes in full-duplex and half-duplex communication mo des. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification support s basic sd card/mmc modes. both spis can be served by the dma controller. 3.16.4 universal se rial bus (usb) the stm32l15xxx embeds a usb device periphe ral compatible with the usb full speed 12 mbit/s. the usb interface implements a full speed (12 mbit/s) functi on interface. it has software-configurable endpoint setting and supports suspend/resume. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator).
docid17659 rev 9 29/131 stm32l151x6/8/b, stm32l152x6/8/b functional overview 47 3.17 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.18 development support serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag jtms and jtck pins are shared with swdat and swclk, respectively, and a specific sequence on the jtms pin is us ed to switch between jtag-dp and sw-dp. the jtag port can be permanently disabled with a jtag fuse. embedded trace macrocell? the arm embedded trace macroce ll provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32l15xxx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instru ction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from co mmon development tool vendors. it operates with third party debugger software tools.
pin descriptions stm32l151x 6/8/b, stm32l152x6/8/b 30/131 docid17659 rev 9 4 pin descriptions figure 3. stm32l15xvx ufbga100 ballout 1. this figure shows the package top view. ai17096f a b e d c f g h j k l m pe3 osc_in pc15 osc32_out pc14 pc13 wkup2 pe4 osc_out pc0 vssa vref- vref+ vdda pe1 pe5 pe2 pe6 wukp3 vlcd vss_5 vdd_5 nrst pc1 pc3 pa0 wkup1 pa1 pb8 pe0 pb9 vss_3 vss_4 vdd_4 pc2 pa2 pa3 pa4 boot0 pb7 vdd_3 pa5 pa6 pa7 pd7 pb6 pb5 pc4 pc5 pb0 pd5 pd6 pb2 pb1 pb4 pd4 pe8 pe7 pb3 pd3 pd2 pd9 pe10 pe9 pa15 pd1 pd0 pd8 pe12 pe11 pa14 pc12 pc11 pc8 pa9 pd15 pd12 pb15 pb10 pe13 pa13 pc10 ph2 pa8 pc7 pd14 pd11 pb14 pb11 pe14 vss_2 vdd_2 pa12 pa11 pa10 pc9 pc6 pd13 pd10 pb13 pb12 pe15 vss_1 vdd_1 2 3 4 5 6 7 8 9 10 11 12 1 ph0 ph1 osc32_in
docid17659 rev 9 31/131 stm32l151x6/8/b, stm32l152x6/8/b pin descriptions 47 figure 4. stm32l15xvx lqfp100 pinout 1. this figure shows the package top view. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vdd_2 vss_2 ph2 pa13 pa12 pa11 pa10 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pe2 pe3 pe4 pe5 pe6-wkup3 v lcd pc13-wkup2 pc14-osc32_in pc15-osc32_out vss_5 vdd_5 ph0-osc_in ph1-osc_out nrst pc0 pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p1 pa 1 pa 2 ai15692c lqfp100 pa8 pa9
pin descriptions stm32l151x 6/8/b, stm32l152x6/8/b 32/131 docid17659 rev 9 figure 5. stm32l15xrx tfbga64 ballout 1. this figure shows the package top view. ai16090c pb2 pc14- o s c 3 2_in pa7 pa4 pa2 pa15 pb11 pb1 pa6 pa 3 h pb10 pc5 pc4 d pa 8 pa9 boot0 pb 8 c pc9 pa11 pb6 pc12 v dda pb9 b pa12 pc10 pc15- o s c 3 2_out pb 3 pd2 a 8 7 6 5 4 3 2 1 v ss _4 o s c_in o s c_out v dd_4 g f e pc2 v ref+ pc1 3 - wkup2 pb4 pa1 3 pa14 pb7 pb5 v ss _ 3 pc7 pc 8 pc0 nr s t pc1 pb0 pa5 pb14 v dd_2 v dd_ 3 pb1 3 vlcd pc11 pa10 v ss _2 v ss _1 pc6 v ss a pa1 v dd_1 pb15 pb12 pa0-wkup1 ph0- ph1-
docid17659 rev 9 33/131 stm32l151x6/8/b, stm32l152x6/8/b pin descriptions 47 figure 6. stm32l15xrx lqfp64 pinout 1. this figure shows the package top view. figure 7. stm32l15xcx lqfp48 pinout 1. this figure shows the package top view. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v lcd pc13-wkup2 pc14-osc32_in pc15-osc32_out ph0 -osc_in ph1- osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p1 pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai15693c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pb15 pb14 pb13 pb12 v lcd pc13-wkup2 pc14-osc32_in pc15-osc32_out ph0-osc_in ph1-osc_out nrst vssa vdda pa 0 -w k u p1 pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa 1 5 pa 1 4 lqfp48 ai15694 c
pin descriptions stm32l151x 6/8/b, stm32l152x6/8/b 34/131 docid17659 rev 9 figure 8. stm32l15xcx ufqfpn48 pinout 1. this figure shows the package top view. v ss_3 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 48 47 46 45 44 43 42 41 40 1 36 v dd_2 2 35 v ss_2 3 34 pa13 4 ufqfpn48 33 pa12 v ssa 5 32 pa11 v dda 6 31 pa10 pa0-wkup1 7 30 pa9 pa1 8 29 pa8 pa2 9 28 v dd_1 13 14 15 16 17 18 19 20 21 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 v ss_1 ai15695d 10 11 12 27 26 25 22 23 24 39 38 37 pb10 pb11 pb15 pb14 pb13 pb12 v lcd pc13-wkup2 pc14-osc32_in pc15-osc32_out ph0-osc_in ph1-osc_out nrst pb9 pb8 v dd_3
docid17659 rev 9 35/131 stm32l151x6/8/b, stm32l152x6/8/b pin descriptions 47 table 7. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tc standard 3.3 v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers
pin descriptions stm32l151x 6/8/b, stm32l152x6/8/b 36/131 docid17659 rev 9 table 8. stm32l15xxx pin definitions pins pin name pin type (1) i/o structure main function (2) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or ufqfpn48 1 - - b2 - pe2 i/o ft pe2 tracec lk/lcd_seg38/tim3_etr 2 - - a1 - pe3 i/o ft pe3 trac ed0/lcd_seg39/tim3_ch1 3 - - b1 - pe4 i/o ft pe4 traced1/tim3_ch2 4 - - c2 - pe5 i/o ft pe5 traced2/tim9_ch1 5 - - d2 - pe6-wkup3 i/o ft pe6 traced3/wkup3/tim9_ch2 61b2e21 v lcd (3) sv lcd - 72a2c12 pc13- wkup2 i/o ft pc13 rtc_tamp1/rtc_ts/rtc_out/wkup2 83a1d13 pc14- osc32_in (4) i/o tc pc14 osc32_in 94b1e14 pc15- osc32_out (4) i/o tc pc15 osc32_out 10 - - f2 - v ss_5 s- v ss_5 - 11 - - g2 - v dd_5 s- v dd_5 - 12 5 c1 f1 5 ph0- osc_in (5) i/o tc ph0 osc_in 13 6 d1 g1 6 ph1- osc_out i/o tc ph1 osc_out 14 7 e1 h2 7 nrst i/o rst nrst - 15 8 e3 h1 - pc0 i/o ft pc0 adc_in10/lcd_seg18/comp1_inp 16 9 e2 j2 - pc1 i/o ft pc1 adc_in11/lcd_seg19/comp1_inp 17 10 f2 j3 - pc2 i/o ft pc2 adc_in12/lcd_seg20/comp1_inp 18 11 - (6) k2 - pc3 i/o tc pc3 adc_in13/lcd_seg21/comp1_inp 19 12 f1 j1 8 v ssa s- v ssa - 20 - - k1 - v ref- s- v ref- - 21 - g1 (6) l1 - v ref+ s- v ref+ -
docid17659 rev 9 37/131 stm32l151x6/8/b, stm32l152x6/8/b pin descriptions 47 22 13 h1 m1 9 v dda s- v dda - 23 14 g2 l2 10 pa0-wkup1 i/o ft pa0 wkup1/usart2_cts/adc_in0/ tim2_ch1_etr/comp1_inp 24 15 h2 m2 11 pa1 i/o ft pa1 usart2_rts/adc_in1/tim2_ch2/ lcd_seg0/comp1_inp 25 16 f3 k3 12 pa2 i/o ft pa2 usart2_tx/adc_in2/tim2_ch3/ tim9_ch1/lcd_seg1/comp1_inp 26 17 g3 l3 13 pa3 i/o tc pa3 usart2_rx/adc_in3/tim2_ch4/ tim9_ch2/lcd_seg2/comp1_inp 27 18 c2 e3 - v ss_4 s- v ss_4 - 28 19 d2 h3 - v dd_4 s- v dd_4 - 29 20 h3 m3 14 pa4 i/o tc pa4 spi1_nss/usart2_ck/ adc_in4/dac_out1/comp1_inp 30 21 f4 k4 15 pa5 i/o tc pa5 spi1_sck/adc_in5/ dac_out2/tim2_ch1_etr/comp1_inp 31 22 g4 l4 16 pa6 i/o ft pa6 spi1_miso/adc_in6/tim3_ch1/ lcd_seg3/tim10_ch1/comp1_inp 32 23 h4 m4 17 pa7 i/o ft pa7 spi1_mosi/adc_in7/tim3_ch2/ lcd_seg4/tim11_ch1/comp1_inp 33 24 h5 k5 - pc4 i/o ft pc4 adc_in14/lcd_seg22/comp1_inp 34 25 h6 l5 - pc5 i/o ft pc5 adc_in15/lcd_seg23/comp1_inp 35 26 f5 m5 18 pb0 i/o tc pb0 adc_in8/tim3_ch3/lcd_seg5/ comp1_inp/vref_out 36 27 g5 m6 19 pb1 i/o ft pb1 adc_in9/tim3_ch4/lcd_seg6/ comp1_inp/vref_out 37 28 g6 l6 20 pb2 i/o ft pb2/boot1 - 38 - - m7 - pe7 i/o tc pe7 adc_in22/comp1_inp 39 - - l7 - pe8 i/o tc pe8 adc_in23/comp1_inp 40 - - m8 - pe9 i/o tc pe9 adc_in24/tim2_ch1_etr/comp1_inp table 8. stm32l15xxx pin definitions (continued) pins pin name pin type (1) i/o structure main function (2) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or ufqfpn48
pin descriptions stm32l151x 6/8/b, stm32l152x6/8/b 38/131 docid17659 rev 9 41 - - l8 - pe10 i/o tc pe10 adc_in25/tim2_ch2/comp1_inp 42 - - m9 - pe11 i/o ft pe11 tim2_ch3 43 - - l9 - pe12 i/o ft pe12 tim2_ch4/spi1_nss 44 - - m10 - pe13 i/o ft pe13 spi1_sck 45 - - m11 - pe14 i/o ft pe14 spi1_miso 46 - - m12 - pe15 i/o ft pe15 spi1_mosi 47 29 g7 l10 21 pb10 i/o ft pb10 i2c2_scl/usart3_tx/tim2_ch3/ lcd_seg10 48 30 h7 l11 22 pb11 i/o ft pb11 i2c2_sda/usart3_rx/tim2_ch4/lcd_se g11 49 31 d6 f12 23 v ss_1 s- v ss_1 - 50 32 e6 g12 24 v dd_1 s- v dd_1 - 51 33 h8 l12 25 pb12 i/o ft pb12 spi2_nss/i2c2_smba/usart3_ck/ lcd_seg12/adc_in18/comp1_inp/ tim10_ch1 52 34 g8 k12 26 pb13 i/o ft pb13 spi2_sck/usart3_cts/lcd_seg13/ adc_in19/comp1_inp/tim9_ch1 53 35 f8 k11 27 pb14 i/o ft pb14 spi2_miso/usart3 _rts/lcd_seg14/ adc_in20/comp1_inp/tim9_ch2 54 36 f7 k10 28 pb15 i/o ft pb15 spi2_mosi/lcd_seg15/ adc_in21/comp1_inp/tim11_ch1/ rtc_refin 55 - - k9 - pd8 i/o ft pd8 usart3_tx/lcd_seg28 56 - - k8 - pd9 i/o ft pd9 usart3_rx/lcd_seg29 57 - - j12 - pd10 i/o ft pd1 0 usart3_ck/lcd_seg30 58 - - j11 - pd11 i/o ft pd11 usart3_cts/lcd_seg31 59 - - j10 - pd12 i/o ft pd12 tim4_ch1/usart3_rts/lcd_seg32 60 - - h12 - pd13 i/o ft pd13 tim4_ch2/lcd_seg33 table 8. stm32l15xxx pin definitions (continued) pins pin name pin type (1) i/o structure main function (2) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or ufqfpn48
docid17659 rev 9 39/131 stm32l151x6/8/b, stm32l152x6/8/b pin descriptions 47 61 - - h11 - pd14 i/o ft pd14 tim4_ch3/lcd_seg34 62 - - h10 - pd15 i/o ft pd15 tim4_ch4/lcd_seg35 63 37 f6 e12 - pc6 i/o ft pc6 tim3_ch1/lcd_seg24 64 38 e7 e11 - pc7 i/o ft pc7 tim3_ch2/lcd_seg25 65 39 e8 e10 - pc8 i/o ft pc8 tim3_ch3/lcd_seg26 66 40 d8 d12 - pc9 i/o ft pc9 tim3_ch4/lcd_seg27 67 41 d7 d11 29 pa8 i/o ft pa8 usart1_ck/mco/lcd_com0 68 42 c7 d10 30 pa9 i/o ft pa9 usart1_tx/lcd_com1 69 43 c6 c12 31 pa10 i/o ft pa10 usart1_rx/lcd_com2 70 44 c8 b12 32 pa11 i/o ft pa11 usart1_cts/usb_dm/spi1_miso 71 45 b8 a12 33 pa12 i/o ft pa12 usart1_rts/usb_dp/spi1_mosi 72 46 a8 a11 34 pa13 i/o ft jtms/ swdat - 73 - - c11 - ph2 i/o ft ph2 - 74 47 d5 f11 35 v ss_2 s- v ss_2 - 75 48 e5 g11 36 v dd_2 s- v dd_2 - 76 49 a7 a10 37 pa14 i/o ft jtck /swclk - 77 50 a6 a9 38 pa15 i/o ft jtdi tim2_ch1_etr/pa15/spi1_nss/ lcd_seg17 78 51 b7 b11 - pc10 i/o ft pc10 usart3_tx/lcd_ seg28/lcd_seg40/ lcd_com4 79 52 b6 c10 - pc11 i/o ft pc11 usart3_rx/lcd_seg29/lcd_seg41/ lcd_com5 80 53 c5 b10 - pc12 i/o ft pc12 usart3_ck/lcd_seg30/lcd_seg42/ lcd_com6 81 - - c9 - pd0 i/o ft pd0 spi2_nss/tim9_ch1 82 - - b9 - pd1 i/o ft pd1 spi2_sck table 8. stm32l15xxx pin definitions (continued) pins pin name pin type (1) i/o structure main function (2) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or ufqfpn48
pin descriptions stm32l151x 6/8/b, stm32l152x6/8/b 40/131 docid17659 rev 9 83 54 b5 c8 - pd2 i/o ft pd2 tim3_etr/lcd_seg31/lcd_seg43/ lcd_com7 84 - - b8 - pd3 i/o ft pd3 usart2_cts/spi2_miso 85 - - b7 - pd4 i/o ft pd4 usart2_rts/spi2_mosi 86 - - a6 - pd5 i/o ft pd5 usart2_tx 87 - - b6 - pd6 i/o ft pd6 usart2_rx 88 - - a5 - pd7 i/o ft pd7 usart2_ck/tim9_ch2 89 55 a5 a8 39 pb3 i/o ft jtdo tim2_ch2/pb3/spi 1_sck/comp2_inm/ lcd_seg7 90 56 a4 a7 40 pb4 i/o ft njtrst tim3_ch1/pb4/spi1_ miso/comp2_inp/ lcd_seg8 91 57 c4 c5 41 pb5 i/o ft pb5 i2c1_smba/tim3_ch2/spi1_mosi/ comp2_inp/lcd_seg9 92 58 d3 b5 42 pb6 i/o ft pb6 i2c1_scl/tim4_ch1/usart1_tx 93 59 c3 b4 43 pb7 i/o ft pb7 i2c1_sda/tim4_ch2/usart1_rx/pvd_in 94 60 b4 a4 44 boot0 i b boot0 - 95 61 b3 a3 45 pb8 i/o ft pb8 tim4_ch3/i2c1_scl/lcd_seg16/ tim10_ch1 96 62 a3 b3 46 pb9 i/o ft pb9 tim4_ch4/i2c1_sda/lcd_com3/ tim11_ch1 97 - - c3 - pe0 i/o ft pe0 tim4_e tr/lcd_seg36/tim10_ch1 98 - - a2 - pe1 i/o ft pe1 lcd_seg37/tim11_ch1 99 63 d4 d3 47 v ss_3 s- v ss_3 - 100 64 e4 c4 48 v dd_3 s- v dd_3 - 1. i = input, o = output, s = supply. 2. function availability depends on the chosen device. for devices having reduced peripher al counts, it is always the lower number of peripheral that is included. for example, if a dev ice has only one spi and two usarts, they will be called spi1 and usart1 & usart2, respectively. refer to table 2 on page 10 . 3. applicable to stm32l152xx devices only. in stm32l151xx devices, th is pin should be connected to v dd . table 8. stm32l15xxx pin definitions (continued) pins pin name pin type (1) i/o structure main function (2) (after reset) alternate functions lqfp100 lqfp64 tfbga64 ufbga100 lqfp48 or ufqfpn48
docid17659 rev 9 41/131 stm32l151x6/8/b, stm32l152x6/8/b pin descriptions 47 4. the pc14 and pc15 i/os are only configured as osc32_in/os c32_out when the lse oscillator is on (by setting the lseon bit in the rcc_csr register). the lse oscillator pins osc32_in/osc32_out c an be used as general-purpose pc14/pc15 i/os, respectively, when the lse oscillator is off (after reset, the lse oscillator is off). the lse has priority ove r the gpio function. for more details, refer to using th e osc32_in/osc32_out pins as gpio pc14/pc15 port pins section in the stm32l1xxxx reference manual (rm0038). 5. the ph0 and ph1 i/os are only configured as osc_in/osc_o ut when the hse oscillator is on (by setting the hseon bit in the rcc_cr register). the hse oscillator pins osc_in /osc_out can be used as general-purpose ph0/ph1 i/os, respectively, when the hse oscillator is off (after reset, the hse oscillator is off). the hse has priority over the gpio function. 6. unlike in the lqfp64 package, there is no pc3 in the tfbga64 package. the v ref+ functionality is provided instead.
pin descriptions stm32l151x6/8/b, stm32l152x6/8/b 42/131 docid17659 rev 9 table 9. alternate function input/output port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afi o8 afi o9 afio10 afio11 afio 12 afio 13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usb lcd n/a n/a ri system boot0boot0 -- - - ----------- nrst nrst - - - - - - - - - - - - - - - pa0- wkup1 wkup1 tim2_ch1 _etr ----- usart2_ cts - - - - - - timx_ic1 eventout pa1 - tim2_ch2 - - - - - usart2_ rts - - - [seg0] - - timx_ic2 eventout pa2 - tim2_ch3 - tim9_ch1 - - - usart2_ tx - - - [seg1] - - timx_ic3 eventout pa3 - tim2_ch4 - tim9_ch2 - - - usart2_ rx - - - [seg2] - - timx_ic4 eventout pa4 - - - - - spi1_nss - usart2_ ck - - - - - - timx_ic1 eventout pa5 - tim2_ch1 _etr - - - spi1_sck - - - - - - - - timx_ic2 eventout pa6 - - tim3_ch1 tim10_ch1 - spi1_miso - - - - - [seg3] - - timx_ic3 eventout pa7 - - tim3_ch2 tim11_ch1 - spi1_mosi - - - - - [seg4] - - timx_ic4 eventout pa8mco -- - - -- usart1_ ck - - - [com0] - - timx_ic1 eventout pa9 - -- - - -- usart1_ tx - - - [com1] - - timx_ic2 eventout pa10 - - - - - - - usart1_ rx - - - [com2] - - timx_ic3 eventout pa11 - - - - - spi1_miso - usart1_ cts - - dm - - - timx_ic4 eventout pa12 - - - - - spi1_mosi - usart1_ rts - - dp - - - timx_ic1 eventout pa13 jtms- swdat -- - - ---------timx_ic2eventout
stm32l151x6/8/b, stm32l1 52x6/8/b pin descriptions docid17659 rev 9 43/131 pa14 jtck- swclk -- - - ---------timx_ic3eventout pa15 jtdi tim2_ch1 _etr - - - spi1_nss - - - - - seg17 - - timx_ic4 eventout pb0 - - tim3_ch3 - - - - - - - - [seg5] - - - eventout pb1 - - tim3_ch4 - - - - - - - - [seg6] - - - eventout pb2boot1 -- - - ----------eventout pb3 jtdo tim2_ch2 - - - spi1_sck - - - - - [seg7] - - - eventout pb4 jtrst - tim3_ch1 - - spi1_miso - - - - - [seg8] - - - eventout pb5 - - tim3_ch2 - i2c1_ smba spi1_mosi - - - - - [seg9] - - - eventout pb6 - - tim4_ch1 - i2c1_scl - - usart1_ tx - - - - - - - eventout pb7 - - tim4_ch2 - i2c1_sda - - usart1_ rx - - - - - - - eventout pb8 - - tim4_ch3 tim10_ch1* i2c1_scl - - - - - - seg16 - - - eventout pb9 - - tim4_ch4 tim11_ch1* i2c1_sda - - - - - - [com3] - - - eventout pb10 - tim2_ch3 - - i2c2_scl - - usart3_ tx - - - seg10 - - - eventout pb11 - tim2_ch4 - - i2c2_sda - - usart3_ rx - - - seg11 - - - eventout pb12 - - - tim10_ch1 i2c2_ smba spi2_nss - usart3_ ck - - - seg12 - - - eventout pb13 - - - tim9_ch1 - spi2_sck - usart3_ cts - - - seg13 - - - eventout pb14 - - - tim9_ch2 - spi2_miso - usart3_ rts - - - seg14 - - - eventout pb15 rtc_refin - - tim11_ch1 - spi2_mosi - - - - - seg15 - - - eventout table 9. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afi o8 afi o9 afio10 afio11 afio 12 afio 13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usb lcd n/a n/a ri system
pin descriptions stm32l151x6/8/b, stm32l152x6/8/b 44/131 docid17659 rev 9 pc0 - - - - - - - - - - - seg18 - - timx_ic1 eventout pc1 - - - - - - - - - - - seg19 - - timx_ic2 eventout pc2 - - - - - - - - - - - seg20 - - timx_ic3 eventout pc3 - - - - - - - - - - - seg21 - - timx_ic4 eventout pc4 - - - - - - - - - - - seg22 - - timx_ic1 eventout pc5 - - - - - - - - - - - seg23 - - timx_ic2 eventout pc6 - - tim3_ch1 - - - - - - - - seg24 - - timx_ic3 eventout pc7 - - tim3_ch2 - - - - - - - - seg25 - - timx_ic4 eventout pc8 - - tim3_ch3 - - - - - - - - seg26 - - timx_ic1 eventout pc9 - - tim3_ch4 - - - - - - - - seg27 - - timx_ic2 eventout pc10 - - - - - - - usart3_ tx -- - com4 / seg28 / seg40 - - timx_ic3 eventout pc11 - - - - - - - usart3_ rx -- - com5 / seg29 / seg41 - - timx_ic4 eventout pc12 - - - - - - - usart3_ ck -- - com6 / seg30 / seg42 - - timx_ic1 eventout pc13- wkup2 rtc_tamp1/ rtc_ts/ rtc_out / wkup2 -- - - ---------timx_ic2eventout pc14- osc32_in osc32_in - - - - - - - - - - - - - timx_ic3 eventout pc15- osc32_o ut osc32_out - - - - - - - - - - - - - timx_ic4 eventout table 9. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afi o8 afi o9 afio10 afio11 afio 12 afio 13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usb lcd n/a n/a ri system
stm32l151x6/8/b, stm32l1 52x6/8/b pin descriptions docid17659 rev 9 45/131 pd0 - - - tim9_ch1 - spi2_nss - - - - - - - - timx_ic1 eventout pd1 - - - - - spi2_sck - - - - - - - - timx_ic2 eventout pd2 - - tim3_etr - - - - - - - - com7 / seg31 / seg43 - - timx_ic3 eventout pd3 - - - - - spi2_miso - usart2_ cts - - - - - - timx_ic4 eventout pd4 - - - - - spi2_mosi - usart2_ rts - - - - - - timx_ic1 eventout pd5 - -- - - -- usart2_ tx - - - - - - timx_ic2 eventout pd6 - -- - - -- usart2_ rx - - - - - - timx_ic3 eventout pd7 - - - tim9_ch2 - - - usart2_ ck - - - - - - timx_ic4 eventout pd8 - -- - - -- usart3_ tx - - - - - - timx_ic1 eventout pd9 - -- - - -- usart3_ rx - - - - - - timx_ic2 eventout pd10 - - - - - - - usart3_ ck - - - - - - timx_ic3 eventout pd11 - - - - - - - usart3_ cts - - - - - - timx_ic4 eventout pd12 - - tim4_ch1 - - - - usart3_ rts - - - - - - timx_ic1 eventout pd13 - - tim4_ch2 - - - - - - - - - - - timx_ic2 eventout pd14 - - tim4_ch3 - - - - - - - - - - - timx_ic3 eventout pd15 - - tim4_ch4 - - - - - - - - - - - timx_ic4 eventout pe0 - - tim4_etr tim10_ch1 - - - - - - - - - - timx_ic1 eventout table 9. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afi o8 afi o9 afio10 afio11 afio 12 afio 13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usb lcd n/a n/a ri system
pin descriptions stm32l151x6/8/b, stm32l152x6/8/b 46/131 docid17659 rev 9 pe1 - - tim11_ch1 - - - - - - - - - - timx_ic2 eventout pe2 traceck - tim3_etr - - - - - - - - - - - timx_ic3 eventout pe3 traced0 - tim3_ch1 - - - - - - - - - - - timx_ic4 eventout pe4 traced1 - tim3_ch2 - - - - - - - - - - - timx_ic1 eventout pe5 traced2 - - tim9_ch1* - - - - - - - - - - timx_ic2 eventout pe6 traced3 / wkup3 - - tim9_ch2* - - - - - - - - - - timx_ic3 eventout pe7 - -- - - ---------timx_ic4eventout pe8 - -- - - ---------timx_ic1eventout pe9 - tim2_ch1 _etr - - - - - - - - - - - - timx_ic2 eventout pe10 - tim2_ch2 - - - - - - - - - - - - timx_ic3 eventout pe11 - tim2_ch3 - - - - - - - - - - - - timx_ic4 eventout pe12 - tim2_ch4 - - - spi1_nss - - - - - - - - timx_ic1 eventout pe13 - - - - - spi1_sck - - - - - - - - timx_ic2 eventout pe14 - - - - - spi1_miso - - - - - - - - timx_ic3 eventout pe15 - - - - - spi1_mosi - - - - - - - - timx_ic4 eventout ph0- osc_in osc_in -- - - ----------- ph1- osc_out osc_out - - - - - - - - - - - - - - - ph2 - -- - - ----------- table 9. alternate function input/output (continued) port name digital alternate function number afio0 afio1 afio2 afio3 afio4 afio5 afoi6 afio7 afi o8 afi o9 afio10 afio11 afio 12 afio 13 afio14 afio15 alternate function system tim2 tim3/4 tim9/10/11 i2c1/2 spi1/2 n/a usart 1/2/3 n/a n/a usb lcd n/a n/a ri system
docid17659 rev 9 47/131 stm32l151x6/8/b, stm32l152x6/8/b memory mapping 47 5 memory mapping the memory map is shown in the following figure. figure 9. memory map reserved 0x4000 0000 0x4000 0400 0x4000 0800 0x4000 0c00 0x4000 2800 0x4000 2c00 0x4000 3000 0x4000 3400 0x4000 3800 0x4000 3c00 0x4000 4400 0x4000 4800 0x4000 4c00 0x4001 0c00 0x4001 1000 0x4001 1400 apb memory space crc 0x4002 3800 tim2 reserved 0x4001 0800 0x4001 2400 0x4001 2800 0x4001 3000 0x4001 3400 0x4001 3800 tim3 tim4 rtc wwdg iwdg reserved spi2 usart2 usart3 syscfg tim9 tim11 rese rve d adc reserved usart1 reserved 0x4002 3400 0x4002 0000 0x4001 3c00 0x4000 5400 0x4000 5800 reserved reserved spi1 i2c1 0x4000 6000 0x4000 5c00 pwr tim10 i2c2 reserved exti reserved rcc flash interface reserved reserved reserved 0x4000 6200 0x4000 7000 0x4000 7400 0x4000 7c00 0x4001 0400 0x4002 3c00 0x4002 4000 0x4002 6000 0x4002 6400 0x6000 0000 0xe010 0000 reserved 0xffff ffff usb reg isters dma 0 1 2 3 4 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0x0000 0000 peripherals sram cortex- m3 internal peripherals 0xe010 0000 ai18200b 512 byte usb tim6 tim7 lcd reserved reserved 0x4000 1000 0x4000 1400 0x4000 2400 0x4000 1c00 dac1 & 2 0x4000 7800 port a port b port c port d port e port h reserved 0x4002 3000 0x4002 1800 0x4002 1400 0x4002 1000 0x4002 0c00 0x4002 0800 0x4002 0400 comp + ri flash memory rese rved rese rved 0x0800 0000 0x0801 ffff 0x1ff0 0000 0x1ff8 001f system memory option bytes 0x1ff0 0fff 0x1ff8 0000 aliased to flash or system memory depending on boot pins 0x0000 0000 rese rved data eeprom rese rved 0x0808 0000 0x0808 0fff 0x4001 0000 reserved reserved
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 48/131 docid17659 rev 9 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.6 v (for the 1.65 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ). 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 10. pin loading conditions figure 11. pin input voltage ms19210v1 c = 50 pf mcu pin ms19211v1 mcu pin v in
docid17659 rev 9 49/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.1.6 power supply scheme figure 12. power supply scheme ms32461v1 v dd1/2/.../n analog: rcs, pll,... gp i/os out in kernel logic (cpu, digital & memories) standby-power circuitry (osc32k,rtc, rtc backup registers) wake-up logic n 100 nf + 1 10 f regulator v ss1/2/.../n v dda v ref+ v ref- v ssa adc/ dac level shifter io logic v dd 100 nf + 1 f v ref 100 nf + 1 f v dda
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 50/131 docid17659 rev 9 6.1.7 optional lcd power supply scheme figure 13. optional lcd power supply scheme 1. option 1: lcd power supply is provided by a dedicated vlcd supply source, vsel switch is open. 2. option 2: lcd power supply is provided by the in ternal step-up converter, vsel switch is closed, an external capacitance is needed for co rrect behavior of this converter. 6.1.8 current consumption measurement figure 14. current consum ption measurement scheme ms32462v1 v dd1/2/.../n n x 100 nf + 1 x 10 f step-up converter v ss1/2/.../n v dd 100 nf v lcd v lcd c ext lcd vsel option 1 option 2 ai14126b v dd v dda i dd
docid17659 rev 9 51/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 10: voltage characteristics , table 11: current characteristics , and table 12: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 10. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 11 for maximum allowed injected current values. input voltage on five-volt tolerant pin v ss ? 0.3 v dd +4.0 input voltage on any other pin v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all different ground pins - 50 v ref+ ? v dda allowed voltage difference for v ref+ > v dda -0.4v v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.11 - table 11. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 80 ma i vss total current out of v ss ground lines (sink) (1) 80 i io output current sunk by any i/o and control pin 25 output current sourced by any i/o and control pin - 25 i inj(pin) (2) 2. negative injection disturbs the analog performance of the device. see note in section 6.3.17 . injected current on five-volt tolerant i/o (3) 3. positive current injection is not possible on these i/os. a negative injection is induced by v in v dd while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 10: voltage characteristics for the maximum allowed input voltage values. 5 i inj(pin) total injected current (sum of all i/o and control pins) (5) 5. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). 25
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 52/131 docid17659 rev 9 6.3 operating conditions 6.3.1 general operating conditions table 12. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 13. general operating conditions symbol parameter co nditions min max unit f hclk internal ahb clock frequency - 0 32 mhz f pclk1 internal apb1 clock frequency - 0 32 f pclk2 internal apb2 clock frequency - 0 32 v dd standard operating voltage bor detector disabled 1.65 3.6 v bor detector enabled, at power on 1.8 3.6 bor detector disabled, after power on 1.65 3.6 v dda (1) analog operating voltage (adc and dac not used) must be the same voltage as v dd (2) 1.65 3.6 v analog operating voltage (adc or dac used) 1.8 3.6 v in input voltage on ft pins (3) input voltage on boot0 pin input voltage on any other pin 2.0 v v dd 3.6 v 1.65 v v dd 2.0 v ?0.3 ?0.3 0 ?0.3 5.5 5.25 5.5 v dd +0.3 v p d power dissipation at t a = 85 c (4) bga100 package - 339 mw t a temperature range maximum power dissipation ?40 85 c low power dissipation (5) ?40 105 t j junction temperature range -40 c t a 105c ?40 105 c 1. when the adc is used, refer to table 54: adc characteristics . 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and operation. 3. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. 4. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 12: thermal characteristics on page 52 ). 5. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t j max (see table 12: thermal characteristics on page 52 ).
docid17659 rev 9 53/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.3.2 embedded reset and power control block characteristics the parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in the following table. table 14. embedded reset and power control block characteristics symbol parameter conditions min typ max unit t vdd (1) v dd rise time rate bor detector enabled 0 - s/v bor detector disabled 0 - 1000 v dd fall time rate bor detector enabled 20 - bor detector disabled 0 - 1000 t rsttempo (1) reset temporization v dd rising, bor enabled - 2 3.3 ms v dd rising, bor disabled (2) 0.4 0.7 1.6 v por/pdr power on/power down reset threshold falling edge 1 1.5 1.65 v rising edge 1.3 1.5 1.65 v bor0 brown-out reset threshold 0 falling edge 1.67 1.7 1.74 v rising edge 1.69 1.76 1.8 v bor1 brown-out reset threshold 1 falling edge 1.87 1.93 1.97 rising edge 1.96 2.03 2.07 v bor2 brown-out reset threshold 2 falling edge 2.22 2.30 2.35 rising edge 2.31 2.41 2.44 v bor3 brown-out reset threshold 3 falling edge 2.45 2.55 2.60 rising edge 2.54 2.66 2.7 v bor4 brown-out reset threshold 4 falling edge 2.68 2.8 2.85 rising edge 2.78 2.9 2.95
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 54/131 docid17659 rev 9 v pvd0 programmable voltage detector threshold 0 falling edge 1.8 1.85 1.88 v rising edge 1.88 1.94 1.99 v pvd1 pvd threshold 1 falling edge 1.98 2.04 2.09 rising edge 2.08 2.14 2.18 v pvd2 pvd threshold 2 falling edge 2.20 2.24 2.28 rising edge 2.28 2.34 2.38 v pvd3 pvd threshold 3 falling edge 2.39 2.44 2.48 rising edge 2.47 2.54 2.58 v pvd4 pvd threshold 4 falling edge 2.57 2.64 2.69 rising edge 2.68 2.74 2.79 v pvd5 pvd threshold 5 falling edge 2.77 2.83 2.88 rising edge 2.87 2.94 2.99 v pvd6 pvd threshold 6 falling edge 2.97 3.05 3.09 rising edge 3.08 3.15 3.20 v hyst hysteresis voltage bor0 threshold - 40 - mv all bor and pvd thresholds excepting bor0 -100- 1. guaranteed by characterizati on, not tested in production. 2. valid for device version without bor at power up. please see option "t" in ordering information scheme for more details. table 14. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit
docid17659 rev 9 55/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.3.3 embedded internal reference voltage the parameters given in the following table are based on characterization results, unless otherwise specified. table 15. embedded internal reference voltage calibration values calibration value name description memory address vrefint_cal raw data acquired at temperature of 30 c, v dda = 3 v 0x1ff8 0078-0x1ff8 0079 table 16. embedded internal reference voltage symbol parameter conditions min typ max unit v refint out (1) internal reference voltage ? 40 c < t j < +105 c 1.202 1.224 1.242 v i refint internal reference current consumption - - 1.4 2.3 a t vrefint internal reference startup time - - 2 3 ms v vref_meas v dda and v ref+ voltage during v refint factory measure - 2.99 3 3.01 v a vref_meas accuracy of factory-measured v ref value (2) including uncertainties due to adc and v dda /v ref+ values --5 mv t coeff (3) temperature coefficient ?40 c < t j < +105 c - 20 50 ppm/c 0 c < t j < +50 c - - 20 a coeff (3) long-term stability 1000 hours, t= 25 c - - 1000 ppm v ddcoeff (3) voltage coefficient 3.0 v < v dda < 3.6 v - - 2000 ppm/v t s_vrefint (3)(4) adc sampling time when reading the internal reference voltage -510-s t adc_buf (3) startup time of reference voltage buffer for adc ---10s i buf_adc (3) consumption of reference voltage buffer for adc - - 13.5 25 a i vref_out (3) vref_out output current (5) ---1a c vref_out (3) vref_out output load - - - 50 pf i lpbuf (3) consumption of reference voltage buffer for vref_out and comp - - 730 1200 na v refint_div1 (3) 1/4 reference voltage - 24 25 26 % v refint v refint_div2 (3) 1/2 reference voltage - 49 50 51 v refint_div3 (3) 3/4 reference voltage - 74 75 76 1. tested in production. 2. the internal v ref value is individually meas ured in production and stored in dedicated eeprom bytes. 3. guaranteed by design, not tested in production. 4. shortest sampling time can be determined in the application by multiple iterations. 5. to guarantee less than 1% vref_out deviation.
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 56/131 docid17659 rev 9 6.3.4 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 14: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: ? v dd = 3.6 v ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted depending on f hclk frequency and voltage range ? prefetch and 64-bit access are enabled in configurations with 1 wait state ? when the peripherals are enabled f apb1 = f apb2 = f ahb ? when f hclk > 8 mhz, pll is on and pll inputs are equal to hsi = 8 mhz (if internal clock is used) or hse = 8 mhz (if hse bypass mode is used) the parameters given in table 17 , table 13 and table 14 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 13 .
docid17659 rev 9 57/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 table 17. current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ max (1) unit 55 c 85 c 105 c i dd (run from flash) supply current in run mode, code executed from flash f hse = f hclk up to 16 mhz, included f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 270 400 400 400 a 2 mhz 470 600 600 600 4 mhz 890 1025 1025 1025 range 2, v core =1.5 v vos[1:0] = 10 4 mhz 1 1.3 1.3 1.3 ma 8 mhz 2 2.5 2.5 2.5 16 mhz 3.9 5 5 5 range 1, v core =1.8 v vos[1:0] = 01 8 mhz 2.16 3 3 3 16 mhz 4.8 5.5 5.5 5.5 32 mhz 9.6 11 11 11 hsi clock source (16 mhz) range 2, v core =1.5 v vos[1:0] = 10 16 mhz 4 5 5 5 range 1, v core =1.8 v vos[1:0] = 01 32 mhz 9.4 11 11 11 msi clock, 65 khz range 3, v core =1.2 v vos[1:0] = 11 65 khz 0.05 0.085 0.09 0.1 msi clock, 524 khz 524 khz 0.15 0.185 0.19 0.2 msi clock, 4.2 mhz 4.2 mhz 0.9 1 1 1 1. based on characterization, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register).
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 58/131 docid17659 rev 9 table 18. current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk typ max (1) unit 55 c 85 c 105 c i dd (run from ram) supply current in run mode, code executed from ram, flash switched off f hse = f hclk up to 16 mhz, included f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 200 300 300 300 a 2 mhz 380 500 500 500 4 mhz 720 860 860 860 (3) range 2, v core =1.5 v vos[1:0] = 10 4 mhz 0.9 1 1 1 ma 8 mhz 1.65 2 2 2 16 mhz 3.2 3.7 3.7 3.7 range 1, v core =1.8 v vos[1:0] = 01 8 mhz 2 2.5 2.5 2.5 16 mhz 4 4.5 4.5 4.5 32 mhz 7.7 8.5 8.5 8.5 hsi clock source (16 mhz) range 2, v core =1.5 v vos[1:0] = 10 16 mhz 3.3 3.8 3.8 3.8 range 1, v core =1.8 v vos[1:0] = 01 32 mhz 7.8 9.2 9.2 9.2 msi clock, 65 khz range 3, v core =1.2 v vos[1:0] = 11 65 khz 40 60 60 80 a msi clock, 524 khz 524 khz 110 140 140 160 msi clock, 4.2 mhz 4.2 mhz 700 800 800 820 1. based on characterization, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). 3. tested in production.
docid17659 rev 9 59/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 table 19. current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit 55 c 85 c 105 c i dd (sleep) supply current in sleep mode, code executed from ram, flash switched off f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 80 140 140 140 a 2 mhz 150 210 210 210 4 mhz 280 330 330 330 (3) range 2, v core =1.5 v vos[1:0] = 10 4 mhz 280 400 400 400 8 mhz 450 550 550 550 16 mhz 900 1050 1050 1050 range 1, v core =1.8 v vos[1:0] = 01 8 mhz 550 650 650 650 16 mhz 1050 1200 1200 1200 32 mhz 2300 2500 2500 2500 hsi clock source (16 mhz) range 2, v core =1.5 v vos[1:0] = 10 16 mhz 1000 1100 1100 1100 range 1, v core =1.8 v vos[1:0] = 01 32 mhz 2300 2500 2500 2500 msi clock, 65 khz range 3, v core =1.2 v vos[1:0] = 11 65 khz 30 50 50 60 msi clock, 524 khz 524 khz 50 70 70 80 msi clock, 4.2 mhz 4.2 mhz 200 240 240 250 supply current in sleep mode, code executed from flash f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0] = 11 1 mhz 80 140 140 140 a 2 mhz 150 210 210 210 4 mhz 290 350 350 350 range 2, v core =1.5 v vos[1:0] = 10 4 mhz 300 400 400 400 8 mhz 500 600 600 600 16 mhz 1000 1100 1100 1100 range 1, v core =1.8 v vos[1:0] = 01 8 mhz 550 650 650 650 16 mhz 1050 1200 1200 1200 32 mhz 2300 2500 2500 2500 hsi clock source (16 mhz) range 2, v core =1.5 v vos[1:0] = 10 16 mhz 1000 1100 1100 1100 range 1, v core =1.8 v vos[1:0] = 01 32 mhz 2300 2500 2500 2500
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 60/131 docid17659 rev 9 i dd (sleep) supply current in sleep mode, code executed from flash msi clock, 65 khz range 3, v core =1.2v vos[1:0] = 11 65 khz 40 70 70 80 a msi clock, 524 khz 524 khz 60 90 90 100 msi clock, 4.2 mhz 4.2 mhz 210 250 250 260 1. based on characterization, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register) 3. tested in production table 19. current consumption in sleep mode (continued) symbol parameter conditions f hclk typ max (1) unit 55 c 85 c 105 c
docid17659 rev 9 61/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 table 20. current consumption in low power run mode symbol parameter conditions typ max (1) unit i dd (lp run) supply current in low power run mode all peripherals off, code executed from ram, flash switched off, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 9 12 a t a = 85 c 17.5 24 t a = 105 c 31 46 msi clock, 65 khz f hclk = 65 khz t a = -40 c to 25 c 14 17 t a = 85 c 22 29 t a = 105 c 35 51 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 37 42 t a = 55 c 37 42 t a = 85 c 37 42 t a = 105 c 48 65 all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 24 32 t a = 85 c 33 42 t a = 105 c 48 64 msi clock, 65 khz f hclk = 65 khz t a = -40 c to 25 c 31 40 t a = 85 c 40 48 t a = 105 c 54 70 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 48 58 t a = 55 c 54 63 t a = 85 c 56 65 t a = 105 c 70 90 i dd max (lp run) (2) max allowed current in low power run mode v dd from 1.65 v to 3.6 v - - - 200 1. based on characterization, not tested in production, unless otherwise specified. 2. this limitation is related to the consumption of the cpu core and the peripherals that are powered by the regulator. consumption of the i/os is not included in this limitation.
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 62/131 docid17659 rev 9 table 21. current consumption in low power sleep mode symbol parameter conditions typ max (1) 1. based on characterization, not tested in production, unless otherwise specified. unit i dd (lp sleep) supply current in low power sleep mode all peripherals off, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz flash off t a = -40 c to 25 c 4.4 - a msi clock, 65 khz f hclk = 32 khz flash on t a = -40 c to 25 c 17.5 25 t a = 85 c 22 27 t a = 105 c 31 39 msi clock, 65 khz f hclk = 65 khz, flash on t a = -40 c to 25 c 18 26 t a = 85 c 23 28 t a = 105 c 31 40 msi clock, 131 khz f hclk = 131 khz, flash on t a = -40 c to 25 c 22 30 t a = 55 c 24 32 t a = 85 c 26 34 t a = 105 c 34 45 tim9 and usart1 enabled, flash on, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 17.5 25 t a = 85 c 22 27 t a = 105 c 31 39 msi clock, 65 khz f hclk = 65 khz t a = -40 c to 25 c 18 26 t a = 85 c 23 28 t a = 105 c 31 40 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 22 30 t a = 55 c 24 32 t a = 85 c 26 34 t a = 105 c 34 45 i dd max (lp sleep) max allowed current in low power sleep mode v dd from 1.65 v to 3.6 v ---200
docid17659 rev 9 63/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 table 22. typical and maximum current consumptions in stop mode symbol parameter conditions typ (1) max (1)(2) uni t i dd (stop with rtc) supply current in stop mode with rtc enabled rtc clocked by lsi, regulator in lp mode, hsi and hse off (no independent watchdog) lcd off t a = -40c to 25c v dd = 1.8 v 1.2 2.75 a t a = -40c to 25c 1.4 4 t a = 55c 2.6 6 t a = 85c 4.8 10 t a = 105c 10.2 23 lcd on (static duty) (3) t a = -40c to 25c 3.3 6 t a = 55c 4.5 8 t a = 85c 6.6 12 t a = 105c 13.6 27 lcd on (1/8 duty) (4) t a = -40c to 25c 7.7 10 t a = 55c 8.6 12 t a = 85c 10.7 16 t a = 105c 19.8 40 rtc clocked by lse external clock (32.768 khz), regulator in lp mode, hsi and hse off (no independent watchdog) lcd off t a = -40c to 25c 1.6 4 t a = 55c 2.7 6 t a = 85c 4.8 10 t a = 105c 10.3 23 lcd on (static duty) (3) t a = -40c to 25c 3.6 6 t a = 55c 4.6 8 t a = 85c 6.7 12 t a = 105c 10.9 23 lcd on (1/8 duty) (4) t a = -40c to 25c 7.6 10 t a = 55c 8.6 12 t a = 85c 10.7 16 t a = 105c 19.8 40 rtc clocked by lse (no independent watchdog) (5) lcd off t a = -40c to 25c v dd = 1.8 v 1.45 - t a = -40c to 25c v dd = 3.0 v 1.9 - t a = -40c to 25c v dd = 3.6 v 2.2 -
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 64/131 docid17659 rev 9 i dd (stop) supply current in stop mode (rtc disabled) regulator in lp mode, hsi and hse off, independent watchdog and lsi enabled t a = -40c to 25c 1.1 2.2 a regulator in lp mode, lsi, hsi and hse off (no independent watchdog) t a = -40c to 25c 0.5 0.9 t a = 55c 1.9 5 t a = 85c 3.7 8 t a = 105c 8.9 20 (6) i dd (wu from stop) rms (root mean square) supply current during wakeup time when exiting from stop mode msi = 4.2 mhz v dd = 3.0 v t a = -40c to 25c 2- ma msi = 1.05 mhz 1.45 - msi = 65 khz (7) 1.45 - 1. the typical values are given for v dd = 3.0 v and max values are given for v dd = 3.6 v, unless otherwise specified. 2. based on characterization, not tested in production, unless otherwise specified 3. lcd enabled with external vlcd, static duty, divi sion ratio = 256, all pixels active, no lcd connected 4. lcd enabled with external vlcd, 1/8 duty, 1/3 bias , division ratio = 64, all pixels active, no lcd connected. 5. based on characterization done with a 32.768 khz cr ystal (mc306-g-06q-32.768, manufacturer jfvny) with two 6.8pf loading capacitors. 6. tested in production 7. when msi = 64 khz, the rms current is measured over the first 15 s following the wakeup event. for the remaining time of the wakeup period, the current is similar to the run mode current. table 22. typical and maximum current c onsumptions in stop mode (continued) symbol parameter conditions typ (1) max (1)(2) uni t
docid17659 rev 9 65/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 on-chip peripheral current consumption the current consumption of the on-chip peripher als is given in the following table. the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on table 23. typical and maximum current consumptions in standby mode symbol parameter conditions typ (1) max (1)(2) unit i dd (standby with rtc) supply current in standby mode with rtc enabled rtc clocked by lsi (no independent watchdog) t a = -40 c to 25 c v dd = 1.8 v 0.9 - a t a = -40 c to 25 c 1.1 1.8 t a = 55 c 1.42 2.5 t a = 85 c 1.87 3 t a = 105 c 2.78 5 rtc clocked by lse (no independent watchdog) (3) t a = -40 c to 25 c v dd = 1.8 v 1- t a = -40 c to 25 c 1.33 2.9 t a = 55 c 1.59 3.4 t a = 85 c 2.01 4.3 t a = 105 c 3.27 6.3 i dd (standby) supply current in standby mode with rtc disabled independent watchdog and lsi enabled t a = -40 c to 25 c 1.1 1.6 independent watchdog and lsi off t a = -40 c to 25 c 0.3 0.55 t a = 55 c 0.5 0.8 t a = 85 c 1 1.7 t a = 105 c 2.5 4 (4) i dd (wu from standby) rms supply current during wakeup time when exiting from standby mode - v dd = 3.0 v t a = -40 c to 25 c 1- 1. the typical values are given for v dd = 3.0 v and max values are given for v dd = 3.6 v, unless otherwise specified. 2. based on characterization, not tested in production, unless otherwise specified. 3. based on characterization done with a 32.768 khz crystal (m c306-g-06q-32.768, manufacturer jfvny) with two 6.8pf loading capacitors. 4. tested in production.
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 66/131 docid17659 rev 9 table 24. peripheral current consumption (1) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core =1.8 v vos[1:0] = 01 range 2, v core =1.5 v vos[1:0] = 10 range 3, v core =1.2 v vos[1:0] = 11 low power sleep and run apb1 tim2 13 10.5 8 10.5 a/mhz (f hclk ) tim3 14 12 9 12 tim4 12.5 10.5 8 11 tim6 5.5 4.5 3.5 4.5 tim7 5.5 5 3.5 4.5 lcd 5.553.55 wwdg 4 3.5 2.5 3.5 spi2 5.5 5 4 5 usart2 9 8 5.5 8.5 usart3 10.5 9 6 8 i2c1 8.5 7 5.5 7.5 i2c2 8.5 7 5.5 6.5 usb 12.5 10 6.5 10 pwr 4.5 4 3 3.5 dac 9 7.5 6 7 comp 4.5 4 3.5 4.5 apb2 syscfg & ri 3 2.5 2 2.5 a/mhz (f hclk ) tim9 9 7.5 6 7 tim10 6.5 5.5 4.5 5.5 tim11 7 6 4.5 5.5 adc (2) 11.5 9.5 8 9 spi1 5 4.5 3 4 usart197.567.5
docid17659 rev 9 67/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.3.5 wakeup time from low power mode the wakeup times given in the following table are measured with the msi rc oscillator. the clock source used to wake up the device depends on the current operating mode: ? sleep mode: the clock source is the clock that was set before entering sleep mode ? stop mode: the clock source is the msi o scillator in the range configured before entering stop mode ? standby mode: the clock source is the msi oscillator running at 2.1 mhz ahb gpioa 5 4.5 3.5 4 a/mhz (f hclk ) gpiob 5 4.5 3.5 4.5 gpioc 5 4.5 3.5 4.5 gpiod 5 4.5 3.5 4.5 gpioe 5 4.5 3.5 4.5 gpioh 4 4 3 3.5 crc 1 0.5 0.5 0.5 flash 13 11.5 9 18.5 dma1 12 10 8 10.5 all enabled 166 138 106 130 i dd (rtc) 0.47 a i dd (lcd) 3.1 i dd (adc) (3) 1450 i dd (dac) (4) 340 i dd (comp1) 0.16 i dd (comp2) slow mode 2 fast mode 5 i dd (pvd / bor) (5) 2.6 i dd (iwdg) 0.25 1. data based on differential i dd measurement between all peripherals off an one peripheral with clock enabled, in the following conditions: f hclk = 32 mhz (range 1), f hclk = 16 mhz (range 2), f hclk = 4 mhz (range 3), f hclk = 64khz (low power run/sleep), f apb1 = f hclk , f apb2 = f hclk , default prescaler value for each peripheral. the cpu is in sleep mode in both cases. no i/o pins toggling. not tested in production. 2. hsi oscillator is off for this measure. 3. data based on a differential i dd measurement between adc in reset configur ation and continuous adc conversion (hsi consumption not included). 4. data based on a differential i dd measurement between dac in reset configur ation and continuous dac conversion of v dd /2. dac is in buffered mode, output is left floating. 5. including supply current of internal reference voltage. table 24. peripheral current consumption (1) (continued) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core =1.8 v vos[1:0] = 01 range 2, v core =1.5 v vos[1:0] = 10 range 3, v core =1.2 v vos[1:0] = 11 low power sleep and run
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 68/131 docid17659 rev 9 all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 13 . 6.3.6 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillato r is switched off and the inpu t pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.13 . however, the recommended clock input waveform is shown in figure 15: high-speed external clock source ac timing diagram . table 25. low-power mode wakeup timings symbol parameter conditions typ max (1) 1. based on characterization, not tested in production, unless otherwise specified unit t wusleep wakeup from sleep mode f hclk = 32 mhz 0.36 - s t wusleep_lp wakeup from low power sleep mode f hclk = 262 khz f hclk = 262 khz flash enabled 32 - f hclk = 262 khz flash switched off 34 - t wustop wakeup from stop mode, regulator in run mode f hclk = f msi = 4.2 mhz 8.2 - wakeup from stop mode, regulator in low power mode f hclk = f msi = 4.2 mhz voltage range 1 and 2 8.2 9.3 f hclk = f msi = 4.2 mhz voltage range 3 7.8 11.2 f hclk = f msi = 2.1 mhz 10 12 f hclk = f msi = 1.05 mhz 15.5 20 f hclk = f msi = 524 khz 29 35 f hclk = f msi = 262 khz 53 63 f hclk = f msi = 131 khz 105 118 f hclk = msi = 65 khz 210 237 t wustdby wakeup from standby mode fwu bit = 1 f hclk = msi = 2.1 mhz 50 103 wakeup from standby mode fwu bit = 0 f hclk = msi = 2.1 mhz 2.5 3.2 ms
docid17659 rev 9 69/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 figure 15. high-speed external clock source ac timing diagram table 26. high-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit f hse_ext user external clock source frequency css is on or pll is used 1 832mhz css is off, pll not used 0 v hseh osc_in input pin high level voltage - 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time 12 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 c in(hse) osc_in input capacitance - - 2.6 - pf ducy (hse) duty cycle - 45 - 55 % i l osc_in input leakage current v ss v in v d d --1a ai18232 os c _i n exter nal stm32lxx clock source v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 70/131 docid17659 rev 9 low-speed external user clock generated from an external source the characteristics given in the following table result from tests performed using a low- speed external clock source, and under ambien t temperature and supply voltage conditions summarized in table 13 . figure 16. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 1 to 24 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 28 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization table 27. low-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production symbol parameter conditions min typ max unit f lse_ext user external clock source frequency - 1 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t w(lse) osc32_in high or low time 465 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 10 c in(lse) osc32_in input capacitance - - 0.6 - pf ducy (lse) duty cycle - 45 - 55 % i l osc32_in input leakage current v ss v in v dd --1a ai18233 osc32_in exter nal stm32lxx clock source v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel
docid17659 rev 9 71/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 17 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 28. hse oscillator characteristics (1)(2) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. based on characterization results, not tested in production. symbol parameter condi tions min typ max unit f osc_in oscillator frequency - 1 24 mhz r f feedback resistor - 200 - k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 -20 - pf i hse hse driving current v dd = 3.3 v, v in = v ss with 30 pf load -- 3 ma i dd(hse) hse oscillator power consumption c = 20 pf f osc = 16 mhz -- 2.5 (startup) 0.7 (stabilized) ma c = 10 pf f osc = 16 mhz -- 2.5 (startup) 0.46 (stabilized) g m oscillator transconductance startup 3.5 - - ma /v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal res onator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 1 - ms
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 72/131 docid17659 rev 9 figure 17. hse oscilla tor circuit diagram 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 29 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). table 29. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. based on characterization, not tested in production. symbol parameter conditions min typ max unit f lse low speed external oscillator frequency - - 32.768 - khz r f feedback resistor - - 1.2 - m c (2) 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value for example msiv-tin32.768khz. refer to crystal manufacturer for more details. r s = 30 k -8 -pf i lse lse driving current v dd = 3.3 v, v in = v ss --1.1a i dd (lse) lse oscillator current consumption v dd = 1.8 v - 450 - na v dd = 3.0 v - 600 - v dd = 3.6v - 750 - g m oscillator transconductance - 3 - - a/v t su(lse) (4) 4. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. th is value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 1 - s osc_out osc_in f hse to core c l1 c l2 r f stm32 resonator consumption control g m r m c m l m c o resonator ai18235
docid17659 rev 9 73/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 note: for cl1 and cl2, it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 18 ). cl1 and cl2, are usually the same size. the cr ystal manufacturer typi cally specifies a load capacitance which is the series combination of cl1 and cl2. load capacitance cl has the following formul a: cl = cl1 x cl2 / (cl1 + cl2) + cstray where cstray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and cl2 (15 pf) it is strongly recommended to use a resonator with a load capacitance cl 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resona tor with a load capacitance of cl = 6 pf and cstray = 2 pf, then cl1 = cl2 = 8 pf. figure 18. typical applicati on with a 32.768 khz crystal ai17853 osc32_ou t osc32_in f lse c l1 r f stm32lxx 32.768 kh z resonator c l2 resonator with integrated capacitors bias controlled gain
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 74/131 docid17659 rev 9 6.3.7 internal clock source characteristics the parameters given in the following table ar e derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 13 . high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator table 30. hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency v dd = 3.0 v - 16 - mhz trim (1)(2) 1. the trimming step differs depending on the trimming code. it is usually negativ e on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xe0). hsi user-trimmed resolution trimming code is not a multiple of 16 - 0.4 0.7 % trimming code is a multiple of 16 - - 1.5 % acc hsi (2) 2. based on characterization, not tested in production. accuracy of the factory-calibrated hsi oscillator v dda = 3.0 v, t a = 25 c -1 (3) 3. tested in production. -1 (3) % v dda = 3.0 v, t a = 0 to 55 c -1.5 - 1.5 % v dda = 3.0 v, t a = -10 to 70 c -2 - 2 % v dda = 3.0 v, t a = -10 to 85 c -2.5 - 2 % v dda = 3.0 v, t a = -10 to 105 c -4 - 2 % v dda = 1.65 v to 3.6 v t a = -40 to 105 c -4 - 3 % t su(hsi) (2) hsi oscillator startup time - - 3.7 6 s i dd(hsi) (2) hsi oscillator power consumption - - 100 140 a table 31. lsi oscillator characteristics symbol parameter min typ max unit f lsi (1) 1. tested in production. lsi frequency 26 38 56 khz d lsi (2) 2. this is a deviation for an individual part, once the init ial frequency has been measured. lsi oscillator frequency drift 0c t a 85c -10 - 4 % t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - - 200 s i dd(lsi) (3) lsi oscillator power consumption - 400 510 na
docid17659 rev 9 75/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 multi-speed internal (msi) rc oscillator table 32. msi oscillator characteristics symbol parameter condition typ max unit f msi frequency after factory calibration, done at v dd = 3.3 v and t a = 25 c msi range 0 65.5 - khz msi range 1 131 - msi range 2 262 - msi range 3 524 - msi range 4 1.05 - mhz msi range 5 2.1 - msi range 6 4.2 - acc msi frequency error after factory calibration - 0.5 - % d temp(msi) (1) msi oscillator frequency drift 0 c t a 85 c - 3- % d volt(msi) (1) msi oscillator frequency drift 1.65 v v dd 3.6 v, t a = 25 c --2.5%/v i dd(msi) (2) msi oscillator power consumption msi range 0 0.75 - a msi range 1 1 - msi range 2 1.5 - msi range 3 2.5 - msi range 4 4.5 - msi range 5 8 - msi range 6 15 - t su(msi) msi oscillator startup time msi range 0 30 - s msi range 1 20 - msi range 2 15 - msi range 3 10 - msi range 4 6 - msi range 5 5 - msi range 6, voltage range 1 and 2 3.5 - msi range 6, voltage range 3 5-
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 76/131 docid17659 rev 9 6.3.8 pll characteristics the parameters given in table 33 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 13 . t stab(msi) (2) msi oscillator stabilization time msi range 0 - 40 s msi range 1 - 20 msi range 2 - 10 msi range 3 - 4 msi range 4 - 2.5 msi range 5 - 2 msi range 6, voltage range 1 and 2 -2 msi range 3, voltage range 3 -3 f over(msi) msi oscillator frequency overshoot any range to range 5 -4 mhz any range to range 6 -6 1. this is a deviation for an individual part, once the init ial frequency has been measured. 2. based on characterization, not tested in production. table 32. msi oscillator characteristics (continued) symbol parameter condition typ max unit table 33. pll characteristics symbol parameter value unit min typ max (1) 1. based on characterization, not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 2- 24mhz pll input clock duty cycle 45 - 55 % f pll_out pll output clock 2 - 32 mhz t lock worst case pll lock time pll input = 2 mhz pll vco = 96 mhz - 100 130 s jitter cycle-to-cycle jitter - - 600 ps i dda (pll) current consumption on v dda - 220 450 a i dd (pll) current consumption on v dd - 120 150
docid17659 rev 9 77/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.3.9 memory characteristics the characteristics are given at t a = -40 to 105 c unless otherwise specified. ram memory flash memory and data eeprom table 34. ram and hardware registers symbol parameter conditions min typ max unit vrm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in stop mode or under reset) or in hardware registers (only in stop mode). stop mode (or reset) 1.65 - - v table 35. flash memo ry and data eeprom characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit v dd operating voltage read / write / erase -1.65-3.6v t prog programming time for word or half-page erasing - 3.28 3.94 ms programming - 3.28 3.94 i dd average current during whole program/erase operation t a = 25 c, v dd = 3.6 v -300- a maximum current (peak) during program/erase operation -1.52.5ma
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 78/131 docid17659 rev 9 6.3.10 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 37 . they are based on the ems levels and classes defined in application note an1709. table 36. flash memory, data eeprom endurance and data retention symbol parameter conditions value unit min (1) 1. based on characterization not tested in production. typ max ncyc (2) cycling (erase / write) program memory t a = -40c to 105 c 10 -- kcycles cycling (erase / write) eeprom data memory 300 - - t ret (2) 2. characterization is done according to jedec jesd22-a117. data retention (program memory) after 10 kcycles at t a = 85 c tret = +85 c 30 - - years data retention (eeprom data memory) after 300 kcycles at t a = 85 c 30 - - data retention (program memory) after 10 kcycles at t a = 105 c tret = +105 c 10 - - data retention (eeprom data memory) after 300 kcycles at t a = 105 c 10 - - table 37. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-4 4a
docid17659 rev 9 79/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. table 38. emi characteristics symbol parameter conditions monitored frequency band max vs. frequency range unit 4 mhz voltage range 3 16 mhz voltage range 2 32 mhz voltage range 1 s emi peak level v dd = 3.3 v, t a = 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz 3 -6 -5 dbv 30 to 130 mhz 18 4 -7 130 mhz to 1ghz 15 5 -7 sae emi level 2.5 2 1 -
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 80/131 docid17659 rev 9 6.3.11 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.12 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection acci dentally happens, susceptibility tests are performed on a sample basis during device characterization. table 39. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 ii 500 table 40. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a
docid17659 rev 9 81/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, lcd levels, etc.). the test results are given in table 41 . note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 41. i/o current in jection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on all 5 v tolerant (ft) pins -5 +0 ma injected current on any other pin -5 +5
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 82/131 docid17659 rev 9 6.3.13 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 42 are derived from tests performed under conditions summarized in table 13 . all i/os are cmos and ttl compliant. table 42. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage - - - - 0.3v dd (1) v v ih input high level voltage standard i/o 0.7 v dd -- ft i/o - - v hys i/o schmitt trigger voltage hysteresis (2) standard i/o - 10% v dd (3) - ft i/o - 5% v dd (4) - i lkg input leakage current (5) v ss v in v dd i/os with lcd --50 na v ss v in v dd i/os with analog switches --50 v ss v in v dd i/os with analog switches and lcd --50 v ss v in v dd i/os with usb --tbd ft i/o v dd v in 5v --tbd v ss v in v dd standard i/os --50 r pu weak pull-up equivalent resistor (6)(1) v in = v ss 30 45 60 k r pd weak pull-down equivalent resistor (6) v in = v dd 30 45 60 k c io i/o pin capacitance - - - 5 - pf 1. tested in production 2. hysteresis voltage between schmitt trigger switching leve ls. based on characterization, not tested in production. 3. with a minimum of 200 mv. based on c haracterization, not tested in production. 4. with a minimum of 100 mv. based on c haracterization, not tested in production. 5. the max. value may be exceeded if negative current is injected on adjacent pins. 6. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order).
docid17659 rev 9 83/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 output driving current the gpios (general purpose input/outputs) can si nk or source up to 8 ma, and sink or source up to 20 ma (with the non-standard v ol /v oh specifications given in table 43 . in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 11 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 11 ). output voltage levels unless otherwise specified, the parameters given in table 43 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 13 . all i/os are cmos and ttl compliant. table 43. output voltage characteristics symbol parameter conditions min max unit v ol (1)(2) output low level voltage for an i/o pin i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3)(2) output high level voltage for an i/o pin 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io =+ 4 ma 1.65 v < v dd < 2.7 v -0.45 v oh (3)(4) output high level voltage for an i/o pin v dd -0.45 - v ol (1)(4) output low level voltage for an i/o pin i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v oh (3)(4) output high level voltage for an i/o pin v dd -1.3 - 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 11 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. tested in production. 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 11 and the sum of i io (i/o ports and control pins) must not exceed i vdd . 4. based on characterization data, not tested in production.
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 84/131 docid17659 rev 9 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 19 and table 44 , respectively. unless otherwise specified, the parameters given in table 44 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 13 . table 44. i/o ac characteristics (1) ospeedrx [1:0] bit value (1) symbol parameter conditions min max (2) unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v -400 khz c l = 50 pf, v dd = 1.65 v to 2.7 v -400 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v -625 ns c l = 50 pf, v dd = 1.65 v to 2.7 v -625 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v -2 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v -1 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v -125 ns c l = 50 pf, v dd = 1.65 v to 2.7 v -250 10 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v -10 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v -2 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v -25 ns c l = 50 pf, v dd = 1.65 v to 2.7 v -125
docid17659 rev 9 85/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 figure 19. i/o ac charac teristics definition 6.3.14 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, rpu (see table 45 ). unless otherwise specified, the parameters given in table 45 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 13 . 11 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v -50 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v -8 t f(io)out t r(io)out output rise and fall time c l = 30 pf, v dd = 2.7 v to 3.6 v -5 ns c l = 50 pf, v dd = 1.65 v to 2.7 v -30 -t extipw pulse width of external signals detected by the exti controller -8- 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the stm32l15xxx reference manual for a description of gpio port configuration register. 2. guaranteed by design. not tested in production. 3. the maximum frequency is defined in figure 19 . table 44. i/o ac characteristics (1) (continued) ospeedrx [1:0] bit value (1) symbol parameter conditions min max (2) unit ai14131b 10% 90% 50% t r( i o)out external output on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50 pf t t f(i o)out
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 86/131 docid17659 rev 9 figure 20. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 45 . otherwise the reset will not be taken into account by the device. table 45. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage - - - 0.8 v v ih(nrst) (1) nrst input high level voltage - 1.4 - v ol(nrst) (1) nrst output low level voltage i ol = 2 ma 2.7 v < v dd < 3.6 v -- 0.4 i ol = 1.5 ma 1.65 v < v dd < 2.7 v -- v hys(nrst) (1) nrst schmitt trigger voltage hysteresis --10%v dd (2) 2. 200 mv minimum value mv r pu weak pull-up equivalent resistor (3) 3. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is around 10%. v in = v ss 30 45 60 k v f(nrst) (1) nrst input filtered pulse - - - 50 ns v nf(nrst) (1) nrst input not filtered pulse - 350 - ns ai17854 stm32lxx r pu nrst (2) v dd filter internal reset 0.1 f external reset circuit (1)
docid17659 rev 9 87/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.3.15 tim time r characteristics the parameters given in table 46 are guaranteed by design. refer to section 6.3.13: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). table 46. timx (1) characteristics 1. timx is used as a general term to refer to the tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time -1-t timxclk f timxclk = 32 mhz 31.25 - ns f ext timer external clock frequency on ch1 to ch4 -0f timxclk /2 mhz f timxclk = 32 mhz 0 16 mhz res tim timer resolution - - 16 bit t counter 16-bit counter clock period when internal clock is selected (timer?s prescaler disabled) - 1 65536 t timxclk f timxclk = 32 mhz 0.0312 2048 s t max_count maximum possible count - - 65536 65536 t timxclk f timxclk = 32 mhz - 134.2 s
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 88/131 docid17659 rev 9 6.3.16 communication interfaces i 2 c interface characteristics the stm32l15xxx product line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following rest rictions: sda and scl are not ?true? open- drain i/o pins. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 47 . refer also to section 6.3.12: i/o current injection characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 47. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i2c frequencies. it must be a multiple of 10 mhz to reach the 400 khz maximum i2c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 - 0 900 (3) 3. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. t r(sda) t r(scl) sda and scl rise time - 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf
docid17659 rev 9 89/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 figure 21. i 2 c bus ac waveforms and measurement circuit 1. r s = series protection resistors 2. r p = pull-up resistors 3. v dd_i2c = i2c bus supply 4. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. table 48. scl frequency (f pclk1 = 32 mhz, v dd = v dd_i2c = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed. 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed is 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x801b 300 0x8024 200 0x8035 100 0x00a0 50 0x0140 20 0x0320 ai17855c s tart sda r s r p i 2 c bus r p r s v dd_i2c v dd_i2c stm32l1xx sda scl t f(sda) t r(sda) scl t h(sta) t w(sckh) t w(sckl) t su(sda) t r(sck) t f(sck) t h(sda) s tart repeated s tart t su(sta) t su(sto) stop t su(sta:sto)
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 90/131 docid17659 rev 9 spi characteristics unless otherwise specified, th e parameters given in the following table are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions su mmarized in table 13 . refer to section 6.3.12: i/o current injection char acteristics for more details on the input/output alternate function char acteristics (nss, sck, mosi, miso). table 49. spi characteristics (1) 1. the characteristics above are given for voltage range 1. symbol parameter conditions min max (2) 2. based on characterization, not tested in production. unit f sck 1/t c(sck) spi clock frequency master mode - 16 mhz slave mode - 16 slave transmitter - 12 (3) 3. the maximum spi clock frequency in slave transmitte r mode is given for an spi slave input clock duty cycle (ducy(sck)) ranging between 40 to 60%. t r(sck) (2) t f(sck) (2) spi clock ri se and fall time capacitive load: c = 30 pf - 6 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) nss setup time slave mode 4t hclk - ns t h(nss) nss hold time slave mode 2t hclk - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode t sck /2 ? 5 t sck /2+ 3 t su(mi) (2) data input setup time master mode 5 - t su(si) (2) slave mode 6 - t h(mi) (2) data input hold time master mode 5 - t h(si) (2) slave mode 5 - t a(so) (4) 4. min time is for the minimum time to drive the outpu t and max time is for the maximum time to validate the data. data output access time slave mode 0 3t hclk t v(so) (2) data output valid time slave mode - 33 t v(mo) (2) data output valid time master mode - 6.5 t h(so) (2) data output hold time slave mode 17 - t h(mo) (2) master mode 0.5 -
docid17659 rev 9 91/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 figure 22. spi timing diagram - slave mode and cpha = 0 figure 23. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 92/131 docid17659 rev 9 figure 24. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. usb characteristics the usb interface is usb-if certified (full speed). table 50. usb startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb transceiver startup time 1 s ai14136 sck input cpha= 0 mosi output miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
docid17659 rev 9 93/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 figure 25. usb timings: definition of data signal rise and fall time table 51. usb dc electrical characteristics symbol parameter c onditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 full speed electrical specification, the usb_dp (d+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 v voltage range. -3.03.6v v di (3) 3. guaranteed by characterization, not tested in production. differential input sensitivity i(usb_dp, usb_dm) 0.2 - v v cm (3) differential common mode range includes v di range 0.8 2.5 v se (3) single ended receiver threshold - 1.3 2.0 output levels v ol (4) 4. tested in production. static output level low r l of 1.5 k to 3.6 v (5) 5. r l is the load connected on the usb drivers. -0.3 v v oh (4) static output level high r l of 15 k to v ss (5) 2.8 3.6 table 52. usb: full speed electrical characteristics driver characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v ai14137 t f differen tial data l ines v ss v cr s t r crossover points
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 94/131 docid17659 rev 9 6.3.17 12-bit adc characteristics unless otherwise specified, the parameters given in table 54 are guaranteed by design. table 53. adc clock frequency symbol parameter conditions min max unit f adc adc clock frequency voltage range 1 & 2 2.4 v v dda 3.6 v v ref+ = v dda 0.480 16 mhz v ref+ < v dda v ref+ > 2.4 v 8 v ref+ < v dda v ref+ 2.4 v 4 1.8 v v dda 2.4 v v ref+ = v dda 8 v ref+ < v dda 4 voltage range 3 4 table 54. adc characteristics symbol parameter conditions min typ max unit v dda power supply - 1.8 - 3.6 v v ref+ positive reference voltage 2.4 v v dda 3.6 v v ref+ must be below or equal to v dda 1.8 (1) -v dda v v ref- negative reference voltage - - v ssa -v i vdda current on the v dda input pin - - 1000 1450 a i vref (2) current on the v ref input pin peak 400 700 a average 450 a v ain conversion voltage range (3) -0 (4) -v ref+ v f s 12-bit sampling rate direct channels 0.03 - 1 msps multiplexed channels 0.03 - 0.76 10-bit sampling rate direct channels 0.03 - 1.07 msps multiplexed channels 0.03 - 0.8 8-bit sampling rate direct channels 0.03 - 1.23 msps multiplexed channels 0.03 - 0.89 6-bit sampling rate direct channels 0.03 - 1.45 msps multiplexed channels 0.03 - 1
docid17659 rev 9 95/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 t s sampling time direct channels 2.4 v v dda 3.6 v 0.25 - - s multiplexed channels 2.4 v v dda 3.6 v 0.56 - - direct channels 1.8 v v dda 2.4 v 0.56 - - multiplexed channels 1.8 v v dda 2.4 v 1- - - 4 - 384 1/f adc t conv total conversion time (including sampling time) f adc = 16 mhz 1 - 24.75 s - 4 to 384 (sampling phase) +12 (successive approximation) 1/f adc c adc internal sample and hold capacitor direct channels - 16 - pf multiplexed channels - - f trig external trigger frequency regular sequencer 12-bit conversions - - tconv+1 1/f adc 6/8/10-bit conversions - - tconv 1/f adc f trig external trigger frequency injected sequencer 12-bit conversions - - tconv+2 1/f adc 6/8/10-bit conversions - - tconv+1 1/f adc r ain signal source impedance - - - 50 ? t lat injection trigger conversion latency f adc = 16 mhz 219 - 281 ns -3.5-4.51/f adc t latr regular trigger conversion latency f adc = 16 mhz 156 - 219 ns -2.5-3.51/f adc t stab power-up time - - - 3.5 s 1. the v ref+ input can be grounded iif neither the adc nor the dac are used (this allows to shut down an external voltage reference). 2. the current consumption through v ref is composed of two parameters: - one constant (max 300 a) - one variable (max 400 a), only during sampling time + 2 fi rst conversion pulses. so, peak consumption is 300+400 = 700 a and average c onsumption is 300 + [(4 sampling + 2) /16] x 400 = 450 a at 1msps 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 4: pin descriptions for further details. 4. v ssa or v ref- must be tied to ground. table 54. adc characteristics (continued) symbol parameter conditions min typ max unit
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 96/131 docid17659 rev 9 table 55. adc accuracy (1)(2) symbol parameter tes t conditions min (3) typ max (3) unit et total unadjusted error 2.4 v v dda 3.6 v 2.4 v v ref+ 3.6 v f adc = 8 mhz, r ain = 50 ? t a = -40 to 105 c -24 lsb eo offset error - 1 2 eg gain error - 1.5 3.5 ed differential linearity error - 1 2 el integral linearity error - 1.7 3 enob effective number of bits 2.4 v v dda 3.6 v v dda = v ref+ f adc = 16 mhz, r ain = 50 ? t a = -40 to 105 c 1 khz f input 100 khz 9.2 10 - bits sinad signal-to-noise and distortion ratio 57.5 62 - db snr signal-to-noise ratio 57.5 62 - thd total harmonic distortion -74 -75 - et total unadjusted error 2.4 v v dda 3.6 v 1.8 v v ref+ 2.4 v f adc = 4 mhz, r ain = 50 ? t a = -40 to 105 c -46.5 lsb eo offset error - 2 4 eg gain error - 4 6 ed differential linearity error - 1 2 el integral linearity error - 1.5 3 et total unadjusted error 1.8 v v dda 2.4 v 1.8 v v ref+ 2.4 v f adc = 4 mhz, r ain = 50 ? t a = -40 to 105 c -23 lsb eo offset error - 1 1.5 eg gain error - 1.5 2 ed differential linearity error - 1 2 el integral linearity error - 1 1.5 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting a negativ e current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins whic h may potentially inject negative currents. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.12 does not affect the adc accuracy. 3. based on characterization, not tested in production.
docid17659 rev 9 97/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 figure 26. adc accuracy characteristics figure 27. typical connecti on diagram using the adc 1. refer to table 56: rain max for fadc = 16 mhz for the value of r ain and table 54: adc characteristics for the value of cadc 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = ai17856b stm32lxx v dd ainx il 50 na 0.6 v vt r ain (1) c parasitic v ain 0.6 v vt r adc (1) 12-bit converter c adc (1) sample and hold adc converter
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 98/131 docid17659 rev 9 figure 28. maximum dynamic current consumption on v ref+ supply pin during adc conversion adc clock sampling (n cycles) conversion (12 cycles) i ref+ 300a 700a table 56. r ain max for f adc = 16 mhz (1) ts (cycles) ts (s) r ain max (kohm) multiplexed channels direct channels 2.4 v < v dda < 3.6 v 1.8 v < v dda < 2.4 v 2.4 v < v dda < 3.3 v 1.8 v < v dda < 2.4 v 4 0.25 not allowed not allowed 0.7 not allowed 9 0.5625 0.8 not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 1. guaranteed by design, not tested in production.
docid17659 rev 9 99/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 general pcb design guidelines power supply decoupling should be performed as shown in figure 29 or figure 30 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed as close as possible to the chip. figure 29. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. figure 30. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. v ref+ (see note 1) stm32lxx v dda v ssa /v refC (see note 1) 1 f // 100 nf 1 f // 100 nf ai17857b v ref+ /v dda stm32lxx 1 f // 100 nf v refC /v ssa ai17858a (see note 1) (see note 1)
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 100/131 docid17659 rev 9 6.3.18 dac electri cal specifications data guaranteed by design, not tested in production, unless otherwise specified. table 57. dac characteristics symbol parameter condi tions min typ max unit v dda analog supply voltage - 1.8 - 3.6 v v ref+ reference supply voltage v ref+ must always be below v dda 1.8 - 3.6 v v ref- lower reference voltage - v ssa v i ddvref+ (1) current consumption on v ref+ supply v ref+ = 3.3 v no load, middle code (0x800) - 130 220 a no load, worst code (0x000) - 220 350 a i dda (1) current consumption on v dda supply v dda = 3.3 v no load, middle code (0x800) - 210 320 a no load, worst code (0xf1c) - 320 520 a r l (2) resistive load dac output buffer on 5- - k c l (2) capacitive load - - 50 pf r o output impedance dac output buffer off 6 8 10 k v dac_out voltage on dac_out output dac output buffer on 0.2 - v dda ? 0.2 v dac output buffer off 0.5 - v ref+ ? 1lsb mv dnl (1) differential non linearity (3) c l 50 pf, r l 5 k dac output buffer on -1.5 3 lsb no r load , c l 50 pf dac output buffer off -1.5 3 inl (1) integral non linearity (4) c l 50 pf, r l 5 k dac output buffer on -2 4 no r load , c l 50 pf dac output buffer off -2 4 offset (1) offset error at code 0x800 (5) c l 50 pf, r l 5 k dac output buffer on -10 25 no r load , c l 50 pf dac output buffer off -5 8 offset1 (1) offset error at code 0x001 (6) no r load , c l 50 pf dac output buffer off -1.5 5
docid17659 rev 9 101/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 doffset/dt (1) offset error temperature coefficient (code 0x800) v dda = 3.3v, v ref+ = 3.0v t a = 0 to 50 c dac output buffer off -20 -10 0 v/c v dda = 3.3v, v ref+ = 3.0v t a = 0 to 50 c dac output buffer on 020 50 gain (1) gain error (7) c l 50 pf, r l 5 k dac output buffer on - +0.1 / -0.2% +0.2 / -0.5% % no r load , c l 50 pf dac output buffer off - +0 / -0.2% +0 / -0.4% dgain/dt (1) gain error temperature coefficient v dda = 3.3v, v ref+ = 3.0v t a = 0 to 50 c dac output buffer off -10 -2 0 v/c v dda = 3.3v, v ref+ = 3.0v t a = 0 to 50 c dac output buffer on -40 -8 0 tue (1) total unadjusted error c l 50 pf, r l 5 k dac output buffer on -12 30 lsb no r load , c l 50 pf dac output buffer off -8 12 t settling settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes till dac_out reaches final value 1lsb c l 50 pf, r l 5 k -7 12s update rate max frequency for a correct dac_out change (95% of final value) with 1 lsb variation in the input code c l 50 pf, r l 5 k - - 1 msps t wakeup wakeup time from off state (setting the enx bit in the dac control register) (8) c l 50 pf, r l 5 k -9 15s psrr+ v dda supply rejection ratio (static dc measurement) c l 50 pf, r l 5 k - -60 -35 db 1. data based on characterization results. 2. connected between dac_out and v ssa . 3. difference between two c onsecutive codes - 1 lsb. 4. difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095. table 57. dac characteristics (continued) symbol parameter condi tions min typ max unit
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 102/131 docid17659 rev 9 figure 31. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 6.3.19 temperature sensor characteristics 5. difference between the value measured at code (0x800) and the ideal value = v ref+ /2. 6. difference between the value measured at code (0x001) and the ideal value. 7. difference between ideal slope of the transfer functi on and measured slope computed from code 0x000 and 0xfff when buffer is off, and from code giving 0.2 v and (v dda ? 0.2) v when buffer is on . 8. in buffered mode, the output can overshoot above the final value for low input code (starting from min value). r load c load b u ffered/non- bu ffered dac dac_outx b u ffer(1) 12- b it digit a l to a n a log converter a i17157v2 table 58. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3 v 0x1ff8 007a-0x1ff8 007b ts_cal2 ts adc raw data acquired at temperature of 110 c v dda = 3 v 0x1ff8 007e-0x1ff8 007f table 59. temperature sensor characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by characterizati on, not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope 1.48 1.61 1.75 mv/c v 110 voltage at 110c 5c (2) 2. measured at v dd = 3 v 10 mv. v110 adc conversion result is stored in the ts_cal2 byte. 612 626.8 641.5 mv i dda(temp) (3) current consumption - 3.4 6 a t start (3) 3. guaranteed by design, not tested in production. startup time - - 10 s t s_temp (4)(3) 4. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 10 - -
docid17659 rev 9 103/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.3.20 comparator table 60. comparator 1 characteristics symbol parameter conditions min (1) typ max (1) 1. based on characterization, not tested in production. unit v dda analog supply voltage - 1.65 3.6 v r 400k r 400k value - - 400 - k r 10k r 10k value - - 10 - v in comparator 1 input voltage range -0.6-v dda v t start comparator startup time - - 7 10 s td propagation delay (2) 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. --310 voffset comparator offset - - 3 10 mv d voffset /dt comparator offset variation in worst voltage stress conditions v dda = 3.6 v v in+ = 0 v v in- = v refint t a = 25 c 0 1.5 10 mv/1000 h i comp1 current consumption (3) 3. comparator consumption only. inte rnal reference voltage not included. - - 160 260 na
electrical characteristics stm32 l151x6/8/b, stm32l152x6/8/b 104/131 docid17659 rev 9 table 61. comparator 2 characteristics symbol parameter conditions min typ max (1) 1. based on characterization, not tested in production. unit v dda analog supply voltage - 1.65 - 3.6 v v in comparator 2 input voltage range - 0 - v dda v t start comparator startup time fast mode - 15 20 s slow mode - 20 25 t d slow propagation delay (2) in slow mode 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 1.65 v v dda 2.7 v -1.83.5 2.7 v v dda 3.6 v - 2.5 6 t d fast propagation delay (2) in fast mode 1.65 v v dda 2.7 v -0.8 2 2.7 v v dda 3.6 v - 1.2 4 v offset comparator offset error - - 4 20 mv dthreshold/ dt threshold voltage temperature coefficient v dda = 3.3v t a = 0 to 50 c v- = v refint , 3/4 v refint , 1/2 v refint , 1/4 v refint -15 30 ppm /c i comp2 current consumption (3) 3. comparator consumption only. internal reference voltage (necessary for comparator operation) is not included. fast mode - 3.5 5 a slow mode - 0.5 2
docid17659 rev 9 105/131 stm32l151x6/8/b, stm32l152x6/8/b electrical characteristics 105 6.3.21 lcd controll er (stm32l152xx only) the stm32l152xx embeds a built-in step-up conv erter to provide a constant lcd reference voltage independently from the v dd voltage. an external capacitor c ext must be connected to the v lcd pin to decouple this converter. table 62. lcd controller characteristics symbol parameter min typ max unit v lcd lcd external voltage - - 3.6 v v lcd0 lcd internal reference voltage 0 - 2.6 - v lcd1 lcd internal reference voltage 1 - 2.73 - v lcd2 lcd internal reference voltage 2 - 2.86 - v lcd3 lcd internal reference voltage 3 - 2.98 - v lcd4 lcd internal reference voltage 4 - 3.12 - v lcd5 lcd internal reference voltage 5 - 3.26 - v lcd6 lcd internal reference voltage 6 - 3.4 - v lcd7 lcd internal reference voltage 7 - 3.55 - c ext v lcd external capacitance 0.1 - 2 f i lcd (1) 1. lcd enabled with 3 v internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no lcd connected supply current at v dd = 2.2 v - 3.3 - a supply current at v dd = 3.0 v - 3.1 - r htot (2) 2. guaranteed by design, not tested in production. low drive resistive network overall value 5.28 6.6 7.92 m r l (2) high drive resistive network total value 192 240 288 k v 44 segment/common highest level voltage - - v lcd v v 34 segment/common 3/4 level voltage - 3/4 v lcd - v v 23 segment/common 2/3 level voltage - 2/3 v lcd - v 12 segment/common 1/2 level voltage - 1/2 v lcd - v 13 segment/common 1/3 level voltage - 1/3 v lcd - v 14 segment/common 1/4 level voltage - 1/4 v lcd - v 0 segment/common lowest level voltage 0 - - vxx (3) 3. based on characterization, not tested in production. segment/common level voltage error t a = -40 to 85 c -- 50 mv
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 106/131 docid17659 rev 9 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specification s, grade definitions and prod uct status are available at: www.st.com . ecopack ? is an st trademark.
docid17659 rev 9 107/131 stm32l151x6/8/b, stm32l152x6/8/b package characteristics 130 figure 32. lqfp100 14 x 14 mm, 100-pin low-profile quad flat package outline 1. drawing is not to scale. e identification pin 1 gauge plane 0.25 mm seating plane d d1 d3 e3 e1 e k ccc c c 1 25 26 100 76 75 51 50 1l_me_v3 a2 a a1 l1 l c b a1
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 108/131 docid17659 rev 9 table 63. lqpf100 14 x 14 mm, 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031
docid17659 rev 9 109/131 stm32l151x6/8/b, stm32l152x6/8/b package characteristics 130 figure 33. recommended footprint 1. dimensions are in millimeters. 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906c
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 110/131 docid17659 rev 9 figure 34. lqfp64 10 x 10 mm, 64-pin low-profile quad flat package outline 1. drawing is not to scale. a1 a2 a seating plane ccc c b c c a1 l l1 k gauge plane 0.25 mm identification pin 1 d d1 d3 e 1 16 17 32 33 48 49 64 e3 e1 e 5w_me_v2
docid17659 rev 9 111/131 stm32l151x6/8/b, stm32l152x6/8/b package characteristics 130 figure 35. recommended footprint 1. dimensions are in millimeters. table 64. lqfp64 10 x 10 mm 64-pin low-pr ofile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max typ min max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d3 - 7.500 - - 0.2953 - e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 k 0.0 3.5 7.0 0.0 3.5 7.0 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 112/131 docid17659 rev 9 figure 36. lqfp48 7 x 7 mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. 5b_me_v2 pin 1 identification ccc c c d3 0.25 mm gauge plane b a1 a a2 c a1 l1 l d d1 e3 e1 e e 12 1 13 24 25 36 37 48 seating plane k
docid17659 rev 9 113/131 stm32l151x6/8/b, stm32l152x6/8/b package characteristics 130 figure 37. recommended footprint 1. dimensions are in millimeters. table 65. lqfp48 7 x 7 mm, 48-pin low-prof ile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 114/131 docid17659 rev 9 figure 38. ufqfpn48 7 x 7 mm 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of t he ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. a0b9_me_v3 d pin 1 indentifier laser marking area ee d y d2 e2 exposed pad area z 1 48 detail z r 0.125 typ. 1 48 l c 0.500x45 pin1 corner a seating plane a1 b e ddd detail y t
docid17659 rev 9 115/131 stm32l151x6/8/b, stm32l152x6/8/b package characteristics 130 figure 39. recommended footprint 1. dimensions are in millimeters. table 66. ufqfpn48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 d 6.900 7.000 7.100 0.2717 0.2756 0.2795 e 6.900 7.000 7.100 0.2717 0.2756 0.2795 d2 5.500 5.600 5.700 0.2165 0.2205 0.2244 e2 5.500 5.600 5.700 0.2165 0.2205 0.2244 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 7.30 7.30 0.20 0.30 0.55 0.50 5.80 6.20 6.20 5.60 5.60 5.80 0.75 ai15697 48 1 12 13 24 25 36 37
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 116/131 docid17659 rev 9 figure 40. ufbga100 7 x 7 x 0.6 mm 0.5 mm pitc h, ultra thin fine-pitch ball grid array package outline 1. drawing is not to scale. table 67. ufbga100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 0.6 - - 0.0236 a1 0.05 0.08 0.11 0.002 0.0031 0.0043 a2 0.4 0.45 0.5 0.0157 0.0177 0.0197 a3 0.08 0.13 0.18 0.0031 0.0051 0.0071 a4 0.27 0.32 0.37 0.0106 0.0126 0.0146 b 0.2 0.25 0.3 0.0079 0.0098 0.0118 d 6.95 7 7.05 0.2736 0.2756 0.2776 d1 5.45 5.5 5.55 0.2146 0.2165 0.2185 e 6.95 7 7.05 0.2736 0.2756 0.2776 e1 5.45 5.5 5.55 0.2146 0.2165 0.2185 e - 0.5 - - 0.0197 - f 0.7 0.75 0.8 0.0276 0.0295 0.0315 ddd - - 0.1 - - 0.0039 a0c2_me_v2 seating plane a1 e f f d m ?b (100 balls) a e top view bottom view 1 12 a1 ball identifier e a a2 y x z ddd z d1 e1 eee z y x fff ? ? m m z a3 a4 a1 ball index area
docid17659 rev 9 117/131 stm32l151x6/8/b, stm32l152x6/8/b package characteristics 130 eee - - 0.15 - - 0.0059 fff - - 0.05 - - 0.002 1. values in inches are converted from mm and rounded to 4 decimal digits. table 67. ufbga100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 118/131 docid17659 rev 9 figure 41. tfbga64 - 5.0x5.0x1.2 mm, 0.5 mm pitch, thin fine-pitch ball grid array package outline 1. drawing is not to scale. table 68. tfbga64 5.0x5.0x1.2 mm, 0.5 mm pitch thin fine-pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.200 - - 0.0472 a1 0.150 - - 0.0059 - - a2 - 0.200 - - 0.0079 - a4 - - 0.600 - - 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 d 4.850 5.000 5.150 0.1909 0.1969 0.2028 d1 - 3.500 - - 0.1378 - e 4.850 5.000 5.150 0.1909 0.1969 0.2028 e1 - 3.500 - - 0.1378 - e - 0.500 - - 0.0197 - f - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 r8_me_v3 seating plane a1 ef f d h ?b (64 balls) a e top view bottom view 1 8 e a y x z ddd z d1 e1 eee z y x fff ? ? m m z a2 a4 a1 ball identifier a1 ball index area
docid17659 rev 9 119/131 stm32l151x6/8/b, stm32l152x6/8/b package characteristics 130 eee - - 0.15 - - 0.0059 fff - - 0.05 - - 0.002 1. values in inches are converted from mm and rounded to 4 decimal digits. table 68. tfbga64 5.0x5.0x1.2 mm, 0.5 mm pitch thin fine-pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 120/131 docid17659 rev 9 figure 42. recommended pcb design rules for pads (0.5 mm pitch bga) 1. non solder mask defined (nsmd) pads are recommended 2. 4 to 6 mils solder paste screen printing process pitch 0.5 mm d pad 0.27 mm dsm 0.35 mm typ (depends on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter dpad dsm ai15495
docid17659 rev 9 121/131 stm32l151x6/8/b, stm32l152x6/8/b package characteristics 130 7.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. table 69. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient bga100 - 7 x 7 mm 59 c/w thermal resistance junction-ambient lqfp100 - 14 x 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient tfbga64 - 5 x 5 mm 65 thermal resistance junction-ambient lqfp64 - 10 x 10 mm / 0.5 mm pitch 45 thermal resistance junction-ambient lqfp48 - 7 x 7 mm / 0.5 mm pitch 55 thermal resistance junction-ambient ufqfpn48 - 7 x 7 mm / 0.5 mm pitch 16
package characteristics stm32l151x6/8/b, stm32l152x6/8/b 122/131 docid17659 rev 9 figure 43. thermal resistance 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. pd (mw) temperature(c) 0.00 500.00 1000.00 1500.00 2000.00 2500.00 3000.00 100 75 50 25 0 uqfn48 7x7mm lqfp48 7x7mm lqfp64 10x10mm lqfp100 14x14mm ufbga100 7x7mm .47 'pscjeefobsfb 5+5+nby
docid17659 rev 9 123/131 stm32l151x6/8/b, stm32l152x6/8/b part numbering 130 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 70. ordering information scheme example: stm32 l 151 c 8 t 6 t xxx device family stm32 = arm-based 32-bit microcontroller product type l = low power device subfamily 151: devices without lcd 152: devices with lcd pin count c = 48 pins r = 64 pins v = 100 pins flash memory size 6 = 32 kbytes of flash memory 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory package h = bga t = lqfp u = ufqfpn temperature range 6 = industrial temperature range, ?40 to 85 c options no character = v dd range: 1.8 to 3.6 v and bor enabled t = v dd range: 1.65 to 3.6 v and bor disabled packing tr = tape and reel no character = tray or tube
revision history stm32l151x6/8/b, stm32l152x6/8/b 124/131 docid17659 rev 9 9 revision history table 71. document revision history date revision changes 02-jul-2010 1 initial release. 01-oct-2010 2 removed 5 v tolerance (ft) from pa3, pb0 and pc3 in table 8: stm32l15xxx pin definitions updated table 14: embedded reset and power control block characteristics updated table 16: embedded internal reference voltage added table 53: adc clock frequency updated table 54: adc characteristics 16-dec-2010 3 modified consumptions on page 1 and in section 3.1: low power modes led_seg8 removed on pb6. updated section 6: electric al characteristics vfqfpn48 replaced by ufqfpn48
docid17659 rev 9 125/131 stm32l151x6/8/b, stm32l 152x6/8/b revision history 130 25-feb-2011 4 features : updated value of low-power sleep. section 3.3.2: power supply supervisor : updated note. table 8: stm32l15xxx pin definitions: modified main function (after reset) and alternate function for osc_in and osc_out pins; modified footnote 5; added footnote to osc32_in and osc32_out pins; c1 and d1 removed on pd0 and pd1 pins (tfbga64 column). section 3.11: dac (digital-to-analog converter) : updated bullet list. table 10: voltage characteristics : updated footnote 3 regarding i inj(pin) . table 11: current characteristics : updated footnote 4 regarding positive and negative injection. table 14: embedded reset and power control block characteristics : updated typ and max values for t rsttempo (v dd rising, bor enabled). table 17: current consumption in run mode, code with data processing running from flash on page 57 : removed values for hsi clock source (16 mhz), range 3. table 18: current consumption in run mode, code with data processing running from ram on page 58 : removed values for hsi clock source (16 mhz), range 3. table 19: current consumption in sleep mode on page 59 removed values for hsi clock source (16 mhz), range 3 for both ram and flash; changed units. table 20: current consumption in low power run mode on page 61 : updated parameter and max value of i dd max (lp run). table 21: current consumption in low power sleep mode on page 62 : updated symbol, parameter, and max value of i dd max (lp sleep). table 22: typical and maximum current consumptions in stop mode on page 63 updated values for i dd (stop with rtc) - rtc clocked by lse external clock (32.768 khz), regulator in lp mode, hsi and hse off (no independent watchdog). table 71. document revision history (continued) date revision changes
revision history stm32l151x6/8/b, stm32l152x6/8/b 126/131 docid17659 rev 9 25-feb-2011 4 (continued) updated table 23: typical and maximum current consumptions in standby mode on page 65 (i dd (wu from standby) instead of (i dd (wu from stop). table 25: low-power mode wakeup timings on page 68 : updated condition for wakeup from stop mode, regulator in run mode; updated max values for wakeup from stop mode, regulator in low power mode; updated max values for t wustdby . table 24: peripheral current consumption on page 66 : updated values for column low power sleep and run; updated flash values; renamed adc1 to adc; updated i dd (lcd) value; updated units; added values for i dd (rtc) and i dd (iwdg) ; updated footnote 1 and 3; added foot note 2 concerning adc. table 26: high-speed external user clock characteristics on page 69 : added min value for t w(hse) /t w(hse) osc_in high or low time; added max value for t r(hse) /t f(hse) osc_in rise or fall time; updated i l for typ and max values. table 27: low-speed external user clock characteristics on page 70 : updated max value for i l . table 28: hse oscillator characteristics on page 71 : renamed i 2 as i hse and updated max value; updated max values for i dd(hse) . table 29: lse oscillator characteristics (flse = 32.768 khz) on page 72 : updated max value for i lse . table 30: hsi oscillator characteristics on page 74 : updated some min and max values for acc hsi . table 32: msi oscillator characteristics on page 75 : updated parameter, typ, and max values for d volt(msi) . table 35: flash memory and data eeprom characteristics on page 77 : updated typ values for t prog . table 44: i/o ac characteristics on page 84 : updated some max values for 01, 10, and 11; updated min value; updated footnotes. table 55: adc accuracy on page 96 : updated typ values and some of the test conditions for enob, sinad, snr, and thd. table 57: dac characteristics on page 100 : updated footnote 7 and added footnote 8. updated leakage value in figure 27: typical connection diagram using the adc . added figure 28: maximum dynamic current consumption on vref+ supply pin during adc conversion . added table 56: rain max for fadc = 16 mhz on page 98 figure 29: power supply and reference decoupling (vref+ not connected to vdda) : replaced all 10 nf capacitors with 100 nf capacitors. figure 30: power supply and reference decoupling (vref+ connected to vdda) : replaced 10 nf capacitor with 100 nf capacitor. table 71. document revision history (continued) date revision changes
docid17659 rev 9 127/131 stm32l151x6/8/b, stm32l 152x6/8/b revision history 130 17-june-2011 5 modified 1st page (low power features) added stm32l15xc6 and stm32l15xr6 devices (32 kbytes of flash memory). modified section 3.6: gpios (general -purpose inputs/outputs) on page 22 modified section 6.3: operating conditions on page 52 modified table 55: adc accuracy on page 96 , table 57: dac characteristics on page 100 and table 60: comparator 1 characteristics on page 103 25-jan-2012 6 features : updated internal multispeed low power rc. table 2: ultralow power stm3 2l15xxx device features and peripheral counts : lcd 4x44 and 8x40 available for both 64- and 128-kbyte devices; two comparators available for all devices. table 3: functionalities depending on the operating power supply range : added footnote 1 . figure 8: stm32l15xcx ufqfpn48 pinout : replaced vfqpn48 by ufqfpn48 as name of package. table 8: stm32l15 xxx pin definitions : replaced ph0/ph1 by pc14/pc15. table 9: alternate function input/output : removed event out from ph2 port, afio15 column. table 19: current consumption in sleep mode : updated msi conditions and f hclk . table 20: current consumption in low power run mode : updated some temperature conditions; added footnote 2. table 21: current consumption in low power sleep mode : updated some temperature conditions and on e of the msi clock conditions. table 22: typical and maximum current consumptions in stop mode : updated i dd (wu from stop) parameter. table 23: typical and maximum current consumptions in standby mode : updated i dd (wu from standby) parameter. table 25: low-power mode wakeup timings : updated f hclk value for t wusleep_lp ; updated typical value of parameter ?wakeup from stop mode, regulator in run mode?. table 24: peripheral current consumption : replaced gpiof by gpioh. table 33: pll characteristics : updated ?pll output clock? table 35: flash memory and data eeprom characteristics : updated all information for i dd . figure 19: i/o ac characteristics definition : replaced the falling edge ?t r(io)out ? by ?t f(io)out ?. table 47: i2c characteristics : amended footnote 2. table 54: adc characteristics : updated f s max value for direct channels, 6-bit sampling rate. table 55: adc accuracy : updated the first, third and fourth f adc test condition. table 59: temperature sensor characteristics : updated typ, min, and max values of the t s_temp parameter. table 71. document revision history (continued) date revision changes
revision history stm32l151x6/8/b, stm32l152x6/8/b 128/131 docid17659 rev 9 26-oct-2012 7 updated cover page. updated section 3.10: adc (analog-to-digital converter) updated table 3: functionalities depending on the operating power supply range , added table 4: cpu frequency range depending on dynamic voltage scaling and table 5: working mode-dependent functionalities (from run/active down to standby) . updated table 27: low-speed external user clock characteristics added footnote 2. in table 14: embedded reset and power control block characteristics updated table 22: typical and maximum current consumptions in stop mode and table 23: typical and maximum current consumptions in standby mode updated footnote 4. in table 22: typical and maximum current consumptions in stop mode updated table 44: i/o ac characteristics updated table 47: i2c characteristics updated table 49: spi characteristics updated section 6.3.9: memory characteristics updated ?non-robust? table 54: adc characteristics removed the note ?position of 4.7 f capacitor? in section 6.1.6: power supply scheme updated table 66: ufqfpn48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package mechanical data updated table 65: lqfp48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data added the resistance of tfbga in table 69: thermal characteristics added figure 43: thermal resistance 07-feb-2013 8 removed ahb1/ahb2 in figure 1: ultralow power stm32l15xxx block diagram added iwdg and wwdg rows in table 5: working mode- dependent functionalities (from run/active down to standby) . updated i dd (supply current during wakeup time from standby mode) in table 23: typical and maximum current consumptions in standby mode the comment "hse = 16 mhz(2) (pll on for fhclk above 16 mhz)" replaced by "fhse = fhclk up to 16 mhz included, fhse = fhclk/2 above 16 mhz (pll on)(2)? in table 19: current consumption in sleep mode updated stop mode current to 1.2 a in ultra-low-power platform updated entire section 7: package characteristics removed alternate function ?i2c2_smba? for gpio pin ?ph2? in table 8: stm32l15 xxx pin definitions updated table 27: typical connection diagram using the adc and definition of symbol ?r ain ? in table 54: adc characteristics removed first sentence in i2c interface characteristics table 71. document revision history (continued) date revision changes
docid17659 rev 9 129/131 stm32l151x6/8/b, stm32l 152x6/8/b revision history 130 12-nov-2013 9 changed voltage range 1 minimum to 1.71 v and updated dynamic voltage scaling range in table 3: functionalities depending on the operating power supply range updated lcd and adc features in table 2: ultralow power stm32l15xxx device features and peripheral counts . updated table 3: functionalities depending on the operating power supply range . updated table 5: working mode-dependent functionalities (from run/active down to standby) . updated figure 3: stm32l15xvx ufbga100 ballout added table 7: legend/abbreviations used in the pinout table . updated table 8: stm32l15xxx pin definitions updated figure 10: pin loading conditions and figure 11: pin input voltage . updated figure 12: power supply scheme . replaced ? ? by ? ? in section 6.1.1 and section 6.1.2 . updated table 10: voltage characteristics . updated table 13: general operating conditions . added section 6.1.7: optional lcd power supply scheme . updated table 16: embedded internal reference voltage . added this note in section : high-speed external clock generated from a crystal/ceramic resonator updated section : functional susceptibility to i/o current injection . this section 6.3.5: wakeup time from low power mode was previously a paragraph in section 6.3.4: supply current characteristics . updated f hse conditions in table 17: current consumption in run mode, code with data proces sing running from flash and table 18: current consumption in run mode , code with data processing running from ram . fixed idd unit in table 23: typical and maximum current consumptions in standby mode . this figure 15: high-speed external clock source ac timing diagram was moved up (was previously after figure 16: low-speed external clock source ac timing diagram . updated first sentence in section 6.3.14: nrst pin characteristics . updated table 25: low-power mode wakeup timings title. updated table 26: high-speed external user clock characteristics updated table 28: hse oscillator characteristics and table 29: lse oscillator characteristics (flse = 32.768 khz) . updated section 6.3.11: electrical sensitivity characteristics title. updated table 39: esd absolute maximum ratings . updated table 41: i/o current injection susceptibility and table 42: i/o static characteristics . updated figure 21: i2c bus ac waveforms and measurement circuit . removed any occurrence of ?when 8 pins are sourced at same time? in table 43: output voltage characteristics . updated section link in second paragraph of section 6.3.15: tim timer characteristics . table 71. document revision history (continued) date revision changes
revision history stm32l151x6/8/b, stm32l152x6/8/b 130/131 docid17659 rev 9 12-nov-2013 9 (continued) updated table 54: adc characteristics and figure 27: typical connection diagram using the adc . table 58: temperature sensor calibration values was previously in section 3.10.1: te mperature sensor . updated table 59: temperature sensor characteristics . in table 61: comparator 2 characteristics , parameter dthreshold/dt, replaced any occurrence of ?vref+? by ?v refint ?updated table 63: lqpf100 14 x 14 mm, 100-pin low-profile quad flat package mechanical data , table 64: lqfp64 10 x 10 mm 64-pin low-profile quad flat package mechanical data , table 65: lqfp48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data and table 66: ufqfpn48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch quad flat no-lead package mechanical data . updated figure 33: recommended footprint . updated figure 41: tfbga64 - 5.0x5.0x1.2 mm, 0.5 mm pitch, thin fine-pitch ball grid array package outline title. remove minimum and typical values of a dimension in table 67: ufbga100 7 x 7 x 0.6 mm 0.5 mm pi tch, ultra thin fine-pitch ball grid array package mechanical data deleted second footnote in figure 39: recommended footprint . updated section 8: part numbering title and added first sentence. changed bor disabled option identifier in table 70: ordering information scheme . table 71. document revision history (continued) date revision changes
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